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@@ -0,0 +1,81 @@
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+/*
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+ * arch/arm/plat-orion/mpp.c
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+ *
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+ * MPP functions for Marvell orion SoCs
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/mbus.h>
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+#include <linux/io.h>
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+#include <linux/gpio.h>
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+#include <mach/hardware.h>
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+#include <plat/mpp.h>
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+
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+/* Address of the ith MPP control register */
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+static __init unsigned long mpp_ctrl_addr(unsigned int i,
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+ unsigned long dev_bus)
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+{
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+ return dev_bus + (i) * 4;
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+}
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+
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+
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+void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
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+ unsigned int mpp_max, unsigned int dev_bus)
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+{
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+ unsigned int mpp_nr_regs = (1 + mpp_max/8);
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+ u32 mpp_ctrl[mpp_nr_regs];
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+ int i;
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+
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+ if (!variant_mask)
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+ return;
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+
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+ printk(KERN_DEBUG "initial MPP regs:");
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+ for (i = 0; i < mpp_nr_regs; i++) {
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+ mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus));
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+ printk(" %08x", mpp_ctrl[i]);
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+ }
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+ printk("\n");
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+
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+ for ( ; *mpp_list; mpp_list++) {
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+ unsigned int num = MPP_NUM(*mpp_list);
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+ unsigned int sel = MPP_SEL(*mpp_list);
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+ int shift, gpio_mode;
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+
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+ if (num > mpp_max) {
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+ printk(KERN_ERR "orion_mpp_conf: invalid MPP "
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+ "number (%u)\n", num);
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+ continue;
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+ }
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+ if (!(*mpp_list & variant_mask)) {
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+ printk(KERN_WARNING
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+ "orion_mpp_conf: requested MPP%u config "
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+ "unavailable on this hardware\n", num);
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+ continue;
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+ }
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+
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+ shift = (num & 7) << 2;
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+ mpp_ctrl[num / 8] &= ~(0xf << shift);
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+ mpp_ctrl[num / 8] |= sel << shift;
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+
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+ gpio_mode = 0;
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+ if (*mpp_list & MPP_INPUT_MASK)
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+ gpio_mode |= GPIO_INPUT_OK;
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+ if (*mpp_list & MPP_OUTPUT_MASK)
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+ gpio_mode |= GPIO_OUTPUT_OK;
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+ if (sel != 0)
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+ gpio_mode = 0;
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+ orion_gpio_set_valid(num, gpio_mode);
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+ }
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+
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+ printk(KERN_DEBUG " final MPP regs:");
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+ for (i = 0; i < mpp_nr_regs; i++) {
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+ writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus));
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+ printk(" %08x", mpp_ctrl[i]);
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+ }
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+ printk("\n");
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+}
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