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@@ -1557,6 +1557,96 @@ unsigned long __init find_ecache_flush_span(unsigned long size)
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return ~0UL;
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}
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+unsigned long PAGE_OFFSET;
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+EXPORT_SYMBOL(PAGE_OFFSET);
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+
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+static void __init page_offset_shift_patch_one(unsigned int *insn, unsigned long phys_bits)
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+{
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+ unsigned long final_shift;
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+ unsigned int val = *insn;
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+ unsigned int cnt;
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+
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+ /* We are patching in ilog2(max_supported_phys_address), and
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+ * we are doing so in a manner similar to a relocation addend.
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+ * That is, we are adding the shift value to whatever value
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+ * is in the shift instruction count field already.
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+ */
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+ cnt = (val & 0x3f);
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+ val &= ~0x3f;
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+
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+ /* If we are trying to shift >= 64 bits, clear the destination
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+ * register. This can happen when phys_bits ends up being equal
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+ * to MAX_PHYS_ADDRESS_BITS.
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+ */
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+ final_shift = (cnt + (64 - phys_bits));
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+ if (final_shift >= 64) {
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+ unsigned int rd = (val >> 25) & 0x1f;
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+
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+ val = 0x80100000 | (rd << 25);
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+ } else {
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+ val |= final_shift;
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+ }
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+ *insn = val;
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+
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+ __asm__ __volatile__("flush %0"
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+ : /* no outputs */
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+ : "r" (insn));
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+}
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+
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+static void __init page_offset_shift_patch(unsigned long phys_bits)
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+{
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+ extern unsigned int __page_offset_shift_patch;
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+ extern unsigned int __page_offset_shift_patch_end;
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+ unsigned int *p;
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+
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+ p = &__page_offset_shift_patch;
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+ while (p < &__page_offset_shift_patch_end) {
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+ unsigned int *insn = (unsigned int *)(unsigned long)*p;
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+
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+ page_offset_shift_patch_one(insn, phys_bits);
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+
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+ p++;
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+ }
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+}
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+
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+static void __init setup_page_offset(void)
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+{
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+ unsigned long max_phys_bits = 40;
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+
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+ if (tlb_type == cheetah || tlb_type == cheetah_plus) {
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+ max_phys_bits = 42;
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+ } else if (tlb_type == hypervisor) {
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+ switch (sun4v_chip_type) {
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+ case SUN4V_CHIP_NIAGARA1:
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+ case SUN4V_CHIP_NIAGARA2:
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+ max_phys_bits = 39;
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+ break;
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+ case SUN4V_CHIP_NIAGARA3:
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+ max_phys_bits = 43;
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+ break;
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+ case SUN4V_CHIP_NIAGARA4:
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+ case SUN4V_CHIP_NIAGARA5:
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+ case SUN4V_CHIP_SPARC64X:
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+ default:
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+ max_phys_bits = 47;
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+ break;
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+ }
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+ }
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+
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+ if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
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+ prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
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+ max_phys_bits);
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+ prom_halt();
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+ }
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+
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+ PAGE_OFFSET = PAGE_OFFSET_BY_BITS(max_phys_bits);
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+
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+ pr_info("PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
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+ PAGE_OFFSET, max_phys_bits);
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+
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+ page_offset_shift_patch(max_phys_bits);
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+}
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+
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static void __init tsb_phys_patch(void)
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{
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struct tsb_ldquad_phys_patch_entry *pquad;
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@@ -1763,6 +1853,8 @@ void __init paging_init(void)
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unsigned long real_end, i;
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int node;
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+ setup_page_offset();
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+
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/* These build time checkes make sure that the dcache_dirty_cpu()
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* page->flags usage will work.
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*
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David S. Miller