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@@ -1433,6 +1433,21 @@ static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
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q_vector->eitr = adapter->rx_eitr_param;
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ixgbe_write_eitr(q_vector);
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+ /* If Flow Director is enabled, set interrupt affinity */
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+ if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
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+ (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
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+ /*
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+ * Allocate the affinity_hint cpumask, assign the mask
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+ * for this vector, and set our affinity_hint for
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+ * this irq.
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+ */
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+ if (!alloc_cpumask_var(&q_vector->affinity_mask,
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+ GFP_KERNEL))
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+ return;
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+ cpumask_set_cpu(v_idx, q_vector->affinity_mask);
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+ irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
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+ q_vector->affinity_mask);
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+ }
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}
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if (adapter->hw.mac.type == ixgbe_mac_82598EB)
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@@ -3816,6 +3831,7 @@ void ixgbe_down(struct ixgbe_adapter *adapter)
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u32 rxctrl;
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u32 txdctl;
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int i, j;
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+ int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
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/* signal that we are down to the interrupt handler */
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set_bit(__IXGBE_DOWN, &adapter->state);
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@@ -3854,6 +3870,15 @@ void ixgbe_down(struct ixgbe_adapter *adapter)
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ixgbe_napi_disable_all(adapter);
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+ /* Cleanup the affinity_hint CPU mask memory and callback */
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+ for (i = 0; i < num_q_vectors; i++) {
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+ struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
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+ /* clear the affinity_mask in the IRQ descriptor */
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+ irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
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+ /* release the CPU mask memory */
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+ free_cpumask_var(q_vector->affinity_mask);
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+ }
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+
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if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
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adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
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cancel_work_sync(&adapter->fdir_reinit_task);
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