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@@ -0,0 +1,173 @@
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+/*
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+ * DPLL + CORE_CLK composite clock functions
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+ *
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+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
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+ * Copyright (C) 2004-2010 Nokia Corporation
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+ *
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+ * Contacts:
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+ * Richard Woodruff <r-woodruff2@ti.com>
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+ * Paul Walmsley
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+ *
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+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
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+ * Gordon McNutt and RidgeRun, Inc.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * XXX The DPLL and CORE clocks should be split into two separate clock
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+ * types.
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+ */
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+#undef DEBUG
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+
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+#include <linux/kernel.h>
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+#include <linux/errno.h>
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+#include <linux/clk.h>
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+#include <linux/io.h>
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+
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+#include <plat/clock.h>
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+#include <plat/sram.h>
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+#include <plat/sdrc.h>
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+
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+#include "clock.h"
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+#include "clock2xxx.h"
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+#include "opp2xxx.h"
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+#include "cm.h"
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+#include "cm-regbits-24xx.h"
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+
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+/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
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+
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+/**
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+ * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
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+ * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
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+ *
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+ * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
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+ * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
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+ * (the latter is unusual). This currently should be called with
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+ * struct clk *dpll_ck, which is a composite clock of dpll_ck and
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+ * core_ck.
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+ */
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+unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
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+{
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+ long long core_clk;
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+ u32 v;
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+
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+ core_clk = omap2_get_dpll_rate(clk);
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+
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+ v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
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+ v &= OMAP24XX_CORE_CLK_SRC_MASK;
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+
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+ if (v == CORE_CLK_SRC_32K)
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+ core_clk = 32768;
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+ else
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+ core_clk *= v;
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+
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+ return core_clk;
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+}
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+
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+/*
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+ * Uses the current prcm set to tell if a rate is valid.
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+ * You can go slower, but not faster within a given rate set.
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+ */
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+static long omap2_dpllcore_round_rate(unsigned long target_rate)
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+{
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+ u32 high, low, core_clk_src;
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+
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+ core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
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+ core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
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+
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+ if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
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+ high = curr_prcm_set->dpll_speed * 2;
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+ low = curr_prcm_set->dpll_speed;
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+ } else { /* DPLL clockout x 2 */
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+ high = curr_prcm_set->dpll_speed;
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+ low = curr_prcm_set->dpll_speed / 2;
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+ }
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+
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+#ifdef DOWN_VARIABLE_DPLL
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+ if (target_rate > high)
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+ return high;
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+ else
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+ return target_rate;
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+#else
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+ if (target_rate > low)
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+ return high;
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+ else
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+ return low;
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+#endif
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+
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+}
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+
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+unsigned long omap2_dpllcore_recalc(struct clk *clk)
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+{
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+ return omap2xxx_clk_get_core_rate(clk);
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+}
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+
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+int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
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+{
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+ u32 cur_rate, low, mult, div, valid_rate, done_rate;
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+ u32 bypass = 0;
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+ struct prcm_config tmpset;
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+ const struct dpll_data *dd;
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+
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+ cur_rate = omap2xxx_clk_get_core_rate(dclk);
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+ mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
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+ mult &= OMAP24XX_CORE_CLK_SRC_MASK;
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+
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+ if ((rate == (cur_rate / 2)) && (mult == 2)) {
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+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
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+ } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
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+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
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+ } else if (rate != cur_rate) {
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+ valid_rate = omap2_dpllcore_round_rate(rate);
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+ if (valid_rate != rate)
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+ return -EINVAL;
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+
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+ if (mult == 1)
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+ low = curr_prcm_set->dpll_speed;
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+ else
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+ low = curr_prcm_set->dpll_speed / 2;
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+
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+ dd = clk->dpll_data;
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+ if (!dd)
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+ return -EINVAL;
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+
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+ tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
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+ tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
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+ dd->div1_mask);
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+ div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
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+ tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
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+ tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
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+ if (rate > low) {
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+ tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
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+ mult = ((rate / 2) / 1000000);
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+ done_rate = CORE_CLK_SRC_DPLL_X2;
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+ } else {
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+ tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
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+ mult = (rate / 1000000);
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+ done_rate = CORE_CLK_SRC_DPLL;
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+ }
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+ tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
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+ tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
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+
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+ /* Worst case */
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+ tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
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+
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+ if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
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+ bypass = 1;
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+
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+ /* For omap2xxx_sdrc_init_params() */
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+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
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+
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+ /* Force dll lock mode */
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+ omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
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+ bypass);
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+
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+ /* Errata: ret dll entry state */
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+ omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
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+ omap2xxx_sdrc_reprogram(done_rate, 0);
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+ }
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+
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+ return 0;
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+}
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+
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Paul Walmsley