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@@ -97,70 +97,77 @@ enum prcmu_wakeup_index {
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/*
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* Clock identifiers.
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*/
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-enum prcmu_clock {
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- PRCMU_SGACLK,
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- PRCMU_UARTCLK,
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- PRCMU_MSP02CLK,
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- PRCMU_MSP1CLK,
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- PRCMU_I2CCLK,
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- PRCMU_SDMMCCLK,
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- PRCMU_SPARE1CLK,
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- PRCMU_SLIMCLK,
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- PRCMU_PER1CLK,
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- PRCMU_PER2CLK,
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- PRCMU_PER3CLK,
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- PRCMU_PER5CLK,
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- PRCMU_PER6CLK,
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- PRCMU_PER7CLK,
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- PRCMU_LCDCLK,
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- PRCMU_BMLCLK,
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- PRCMU_HSITXCLK,
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- PRCMU_HSIRXCLK,
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- PRCMU_HDMICLK,
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- PRCMU_APEATCLK,
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- PRCMU_APETRACECLK,
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- PRCMU_MCDECLK,
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- PRCMU_IPI2CCLK,
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- PRCMU_DSIALTCLK,
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- PRCMU_DMACLK,
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- PRCMU_B2R2CLK,
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- PRCMU_TVCLK,
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- PRCMU_SSPCLK,
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- PRCMU_RNGCLK,
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- PRCMU_UICCCLK,
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- PRCMU_PWMCLK,
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- PRCMU_IRDACLK,
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- PRCMU_IRRCCLK,
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- PRCMU_SIACLK,
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- PRCMU_SVACLK,
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- PRCMU_ACLK,
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- PRCMU_HVACLK, /* Ux540 only */
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- PRCMU_G1CLK, /* Ux540 only */
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- PRCMU_SDMMCHCLK,
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- PRCMU_CAMCLK,
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- PRCMU_BML8580CLK,
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- PRCMU_NUM_REG_CLOCKS,
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- PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
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- PRCMU_CDCLK,
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- PRCMU_TIMCLK,
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- PRCMU_PLLSOC0,
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- PRCMU_PLLSOC1,
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- PRCMU_ARMSS,
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- PRCMU_PLLDDR,
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- PRCMU_PLLDSI,
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- PRCMU_DSI0CLK,
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- PRCMU_DSI1CLK,
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- PRCMU_DSI0ESCCLK,
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- PRCMU_DSI1ESCCLK,
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- PRCMU_DSI2ESCCLK,
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- /* LCD DSI PLL - Ux540 only */
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- PRCMU_PLLDSI_LCD,
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- PRCMU_DSI0CLK_LCD,
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- PRCMU_DSI1CLK_LCD,
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- PRCMU_DSI0ESCCLK_LCD,
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- PRCMU_DSI1ESCCLK_LCD,
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- PRCMU_DSI2ESCCLK_LCD,
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-};
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+#define ARMCLK 0
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+#define PRCMU_ACLK 1
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+#define PRCMU_SVAMMCSPCLK 2
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+#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
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+#define PRCMU_SIACLK 3
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+#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
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+#define PRCMU_SGACLK 4
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+#define PRCMU_UARTCLK 5
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+#define PRCMU_MSP02CLK 6
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+#define PRCMU_MSP1CLK 7
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+#define PRCMU_I2CCLK 8
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+#define PRCMU_SDMMCCLK 9
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+#define PRCMU_SLIMCLK 10
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+#define PRCMU_CAMCLK 10 /* DBx540 only. */
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+#define PRCMU_PER1CLK 11
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+#define PRCMU_PER2CLK 12
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+#define PRCMU_PER3CLK 13
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+#define PRCMU_PER5CLK 14
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+#define PRCMU_PER6CLK 15
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+#define PRCMU_PER7CLK 16
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+#define PRCMU_LCDCLK 17
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+#define PRCMU_BMLCLK 18
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+#define PRCMU_HSITXCLK 19
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+#define PRCMU_HSIRXCLK 20
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+#define PRCMU_HDMICLK 21
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+#define PRCMU_APEATCLK 22
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+#define PRCMU_APETRACECLK 23
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+#define PRCMU_MCDECLK 24
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+#define PRCMU_IPI2CCLK 25
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+#define PRCMU_DSIALTCLK 26
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+#define PRCMU_DMACLK 27
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+#define PRCMU_B2R2CLK 28
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+#define PRCMU_TVCLK 29
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+#define SPARE_UNIPROCLK 30
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+#define PRCMU_SSPCLK 31
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+#define PRCMU_RNGCLK 32
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+#define PRCMU_UICCCLK 33
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+#define PRCMU_G1CLK 34 /* DBx540 only. */
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+#define PRCMU_HVACLK 35 /* DBx540 only. */
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+#define PRCMU_SPARE1CLK 36
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+#define PRCMU_SPARE2CLK 37
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+
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+#define PRCMU_NUM_REG_CLOCKS 38
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+
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+#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS
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+#define PRCMU_SYSCLK 39
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+#define PRCMU_CDCLK 40
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+#define PRCMU_TIMCLK 41
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+#define PRCMU_PLLSOC0 42
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+#define PRCMU_PLLSOC1 43
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+#define PRCMU_ARMSS 44
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+#define PRCMU_PLLDDR 45
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+#define PRCMU_BML8580CLK 46
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+
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+/* DSI Clocks */
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+#define PRCMU_PLLDSI 47
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+#define PRCMU_DSI0CLK 48
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+#define PRCMU_DSI1CLK 49
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+#define PRCMU_DSI0ESCCLK 50
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+#define PRCMU_DSI1ESCCLK 51
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+#define PRCMU_DSI2ESCCLK 52
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+
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+/* LCD DSI PLL - Ux540 only */
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+#define PRCMU_PLLDSI_LCD 53
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+#define PRCMU_DSI0CLK_LCD 54
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+#define PRCMU_DSI1CLK_LCD 55
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+#define PRCMU_DSI0ESCCLK_LCD 56
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+#define PRCMU_DSI1ESCCLK_LCD 57
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+#define PRCMU_DSI2ESCCLK_LCD 58
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+
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+#define PRCMU_NUM_CLKS 59
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/**
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* enum prcmu_wdog_id - PRCMU watchdog IDs
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