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@@ -513,6 +513,9 @@ InstructionTLBMiss:
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rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
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ori r1,r1,0xe04 /* clear out reserved bits */
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andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
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+BEGIN_FTR_SECTION
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+ rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
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+END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
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mtspr SPRN_RPA,r1
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mfspr r3,SPRN_IMISS
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tlbli r3
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@@ -587,6 +590,9 @@ DataLoadTLBMiss:
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rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
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ori r1,r1,0xe04 /* clear out reserved bits */
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andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
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+BEGIN_FTR_SECTION
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+ rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
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+END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
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mtspr SPRN_RPA,r1
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mfspr r3,SPRN_DMISS
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tlbld r3
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@@ -655,6 +661,9 @@ DataStoreTLBMiss:
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rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
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li r1,0xe05 /* clear out reserved bits & PP lsb */
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andc r1,r3,r1 /* PP = user? 2: 0 */
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+BEGIN_FTR_SECTION
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+ rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
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+END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
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mtspr SPRN_RPA,r1
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mfspr r3,SPRN_DMISS
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tlbld r3
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