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@@ -266,13 +266,53 @@ static int vic_set_wake(unsigned int irq, unsigned int on)
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#endif /* CONFIG_PM */
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static struct irq_chip vic_chip = {
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- .name = "VIC",
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- .ack = vic_ack_irq,
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- .mask = vic_mask_irq,
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- .unmask = vic_unmask_irq,
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- .set_wake = vic_set_wake,
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+ .name = "VIC",
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+ .ack = vic_ack_irq,
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+ .mask = vic_mask_irq,
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+ .unmask = vic_unmask_irq,
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+ .set_wake = vic_set_wake,
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};
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+static void __init vic_disable(void __iomem *base)
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+{
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+ writel(0, base + VIC_INT_SELECT);
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+ writel(0, base + VIC_INT_ENABLE);
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+ writel(~0, base + VIC_INT_ENABLE_CLEAR);
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+ writel(0, base + VIC_IRQ_STATUS);
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+ writel(0, base + VIC_ITCR);
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+ writel(~0, base + VIC_INT_SOFT_CLEAR);
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+}
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+
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+static void __init vic_clear_interrupts(void __iomem *base)
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+{
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+ unsigned int i;
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+
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+ writel(0, base + VIC_PL190_VECT_ADDR);
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+ for (i = 0; i < 19; i++) {
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+ unsigned int value;
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+
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+ value = readl(base + VIC_PL190_VECT_ADDR);
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+ writel(value, base + VIC_PL190_VECT_ADDR);
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+ }
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+}
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+
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+static void __init vic_set_irq_sources(void __iomem *base,
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+ unsigned int irq_start, u32 vic_sources)
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+{
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+ unsigned int i;
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+
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+ for (i = 0; i < 32; i++) {
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+ if (vic_sources & (1 << i)) {
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+ unsigned int irq = irq_start + i;
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+
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+ set_irq_chip(irq, &vic_chip);
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+ set_irq_chip_data(irq, base);
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+ set_irq_handler(irq, handle_level_irq);
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+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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+ }
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+ }
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+}
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+
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/*
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* The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
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* The original cell has 32 interrupts, while the modified one has 64,
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@@ -287,13 +327,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
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int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
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/* Disable all interrupts initially. */
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-
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- writel(0, base + VIC_INT_SELECT);
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- writel(0, base + VIC_INT_ENABLE);
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- writel(~0, base + VIC_INT_ENABLE_CLEAR);
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- writel(0, base + VIC_IRQ_STATUS);
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- writel(0, base + VIC_ITCR);
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- writel(~0, base + VIC_INT_SOFT_CLEAR);
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+ vic_disable(base);
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/*
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* Make sure we clear all existing interrupts. The vector registers
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@@ -302,13 +336,8 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
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* the second base address, which is 0x20 in the page
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*/
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if (vic_2nd_block) {
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- writel(0, base + VIC_PL190_VECT_ADDR);
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- for (i = 0; i < 19; i++) {
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- unsigned int value;
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+ vic_clear_interrupts(base);
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- value = readl(base + VIC_PL190_VECT_ADDR);
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- writel(value, base + VIC_PL190_VECT_ADDR);
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- }
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/* ST has 16 vectors as well, but we don't enable them by now */
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for (i = 0; i < 16; i++) {
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void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
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@@ -318,16 +347,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
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writel(32, base + VIC_PL190_DEF_VECT_ADDR);
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}
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- for (i = 0; i < 32; i++) {
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- if (vic_sources & (1 << i)) {
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- unsigned int irq = irq_start + i;
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-
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- set_irq_chip(irq, &vic_chip);
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- set_irq_chip_data(irq, base);
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- set_irq_handler(irq, handle_level_irq);
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- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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- }
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- }
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+ vic_set_irq_sources(base, irq_start, vic_sources);
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}
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/**
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@@ -365,37 +385,14 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
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}
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/* Disable all interrupts initially. */
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+ vic_disable(base);
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- writel(0, base + VIC_INT_SELECT);
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- writel(0, base + VIC_INT_ENABLE);
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- writel(~0, base + VIC_INT_ENABLE_CLEAR);
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- writel(0, base + VIC_IRQ_STATUS);
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- writel(0, base + VIC_ITCR);
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- writel(~0, base + VIC_INT_SOFT_CLEAR);
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-
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- /*
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- * Make sure we clear all existing interrupts
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- */
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- writel(0, base + VIC_PL190_VECT_ADDR);
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- for (i = 0; i < 19; i++) {
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- unsigned int value;
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-
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- value = readl(base + VIC_PL190_VECT_ADDR);
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- writel(value, base + VIC_PL190_VECT_ADDR);
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- }
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+ /* Make sure we clear all existing interrupts */
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+ vic_clear_interrupts(base);
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vic_init2(base);
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- for (i = 0; i < 32; i++) {
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- if (vic_sources & (1 << i)) {
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- unsigned int irq = irq_start + i;
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-
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- set_irq_chip(irq, &vic_chip);
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- set_irq_chip_data(irq, base);
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- set_irq_handler(irq, handle_level_irq);
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- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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- }
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- }
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+ vic_set_irq_sources(base, irq_start, vic_sources);
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vic_pm_register(base, irq_start, resume_sources);
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}
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