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@@ -23,9 +23,14 @@
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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+#include <linux/of_platform.h>
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#include <linux/serial_sci.h>
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+#include <linux/sh_dma.h>
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#include <linux/sh_timer.h>
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+#include <linux/dma-mapping.h>
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+#include <mach/dma-register.h>
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#include <mach/r8a7740.h>
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+#include <mach/pm-rmobile.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <asm/mach-types.h>
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@@ -276,6 +281,272 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
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&cmt10_device,
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};
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+/* DMA */
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+static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
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+ {
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+ .slave_id = SHDMA_SLAVE_SDHI0_TX,
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+ .addr = 0xe6850030,
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+ .chcr = CHCR_TX(XMIT_SZ_16BIT),
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+ .mid_rid = 0xc1,
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+ }, {
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+ .slave_id = SHDMA_SLAVE_SDHI0_RX,
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+ .addr = 0xe6850030,
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+ .chcr = CHCR_RX(XMIT_SZ_16BIT),
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+ .mid_rid = 0xc2,
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+ }, {
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+ .slave_id = SHDMA_SLAVE_SDHI1_TX,
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+ .addr = 0xe6860030,
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+ .chcr = CHCR_TX(XMIT_SZ_16BIT),
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+ .mid_rid = 0xc9,
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+ }, {
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+ .slave_id = SHDMA_SLAVE_SDHI1_RX,
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+ .addr = 0xe6860030,
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+ .chcr = CHCR_RX(XMIT_SZ_16BIT),
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+ .mid_rid = 0xca,
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+ }, {
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+ .slave_id = SHDMA_SLAVE_SDHI2_TX,
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+ .addr = 0xe6870030,
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+ .chcr = CHCR_TX(XMIT_SZ_16BIT),
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+ .mid_rid = 0xcd,
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+ }, {
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+ .slave_id = SHDMA_SLAVE_SDHI2_RX,
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+ .addr = 0xe6870030,
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+ .chcr = CHCR_RX(XMIT_SZ_16BIT),
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+ .mid_rid = 0xce,
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+ }, {
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+ .slave_id = SHDMA_SLAVE_FSIA_TX,
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+ .addr = 0xfe1f0024,
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+ .chcr = CHCR_TX(XMIT_SZ_32BIT),
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+ .mid_rid = 0xb1,
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+ }, {
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+ .slave_id = SHDMA_SLAVE_FSIA_RX,
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+ .addr = 0xfe1f0020,
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+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
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+ .mid_rid = 0xb2,
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+ }, {
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+ .slave_id = SHDMA_SLAVE_FSIB_TX,
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+ .addr = 0xfe1f0064,
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+ .chcr = CHCR_TX(XMIT_SZ_32BIT),
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+ .mid_rid = 0xb5,
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+ },
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+};
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+
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+#define DMA_CHANNEL(a, b, c) \
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+{ \
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+ .offset = a, \
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+ .dmars = b, \
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+ .dmars_bit = c, \
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+ .chclr_offset = (0x220 - 0x20) + a \
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+}
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+
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+static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
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+ DMA_CHANNEL(0x00, 0, 0),
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+ DMA_CHANNEL(0x10, 0, 8),
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+ DMA_CHANNEL(0x20, 4, 0),
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+ DMA_CHANNEL(0x30, 4, 8),
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+ DMA_CHANNEL(0x50, 8, 0),
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+ DMA_CHANNEL(0x60, 8, 8),
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+};
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+
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+static struct sh_dmae_pdata dma_platform_data = {
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+ .slave = r8a7740_dmae_slaves,
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+ .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
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+ .channel = r8a7740_dmae_channels,
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+ .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
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+ .ts_low_shift = TS_LOW_SHIFT,
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+ .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
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+ .ts_high_shift = TS_HI_SHIFT,
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+ .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
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+ .ts_shift = dma_ts_shift,
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+ .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
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+ .dmaor_init = DMAOR_DME,
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+ .chclr_present = 1,
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+};
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+
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+/* Resource order important! */
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+static struct resource r8a7740_dmae0_resources[] = {
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+ {
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+ /* Channel registers and DMAOR */
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+ .start = 0xfe008020,
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+ .end = 0xfe00828f,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ /* DMARSx */
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+ .start = 0xfe009000,
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+ .end = 0xfe00900b,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "error_irq",
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+ .start = evt2irq(0x20c0),
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+ .end = evt2irq(0x20c0),
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+ .flags = IORESOURCE_IRQ,
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+ },
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+ {
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+ /* IRQ for channels 0-5 */
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+ .start = evt2irq(0x2000),
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+ .end = evt2irq(0x20a0),
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+/* Resource order important! */
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+static struct resource r8a7740_dmae1_resources[] = {
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+ {
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+ /* Channel registers and DMAOR */
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+ .start = 0xfe018020,
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+ .end = 0xfe01828f,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ /* DMARSx */
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+ .start = 0xfe019000,
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+ .end = 0xfe01900b,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "error_irq",
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+ .start = evt2irq(0x21c0),
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+ .end = evt2irq(0x21c0),
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+ .flags = IORESOURCE_IRQ,
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+ },
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+ {
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+ /* IRQ for channels 0-5 */
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+ .start = evt2irq(0x2100),
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+ .end = evt2irq(0x21a0),
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+/* Resource order important! */
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+static struct resource r8a7740_dmae2_resources[] = {
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+ {
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+ /* Channel registers and DMAOR */
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+ .start = 0xfe028020,
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+ .end = 0xfe02828f,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ /* DMARSx */
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+ .start = 0xfe029000,
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+ .end = 0xfe02900b,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "error_irq",
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+ .start = evt2irq(0x22c0),
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+ .end = evt2irq(0x22c0),
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+ .flags = IORESOURCE_IRQ,
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+ },
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+ {
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+ /* IRQ for channels 0-5 */
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+ .start = evt2irq(0x2200),
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+ .end = evt2irq(0x22a0),
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct platform_device dma0_device = {
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+ .name = "sh-dma-engine",
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+ .id = 0,
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+ .resource = r8a7740_dmae0_resources,
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+ .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
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+ .dev = {
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+ .platform_data = &dma_platform_data,
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+ },
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+};
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+
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+static struct platform_device dma1_device = {
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+ .name = "sh-dma-engine",
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+ .id = 1,
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+ .resource = r8a7740_dmae1_resources,
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+ .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
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+ .dev = {
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+ .platform_data = &dma_platform_data,
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+ },
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+};
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+
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+static struct platform_device dma2_device = {
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+ .name = "sh-dma-engine",
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+ .id = 2,
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+ .resource = r8a7740_dmae2_resources,
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+ .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
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+ .dev = {
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+ .platform_data = &dma_platform_data,
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+ },
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+};
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+
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+/* USB-DMAC */
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+static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
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+ {
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+ .offset = 0,
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+ }, {
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+ .offset = 0x20,
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+ },
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+};
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+
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+static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
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+ {
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+ .slave_id = SHDMA_SLAVE_USBHS_TX,
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+ .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
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+ }, {
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+ .slave_id = SHDMA_SLAVE_USBHS_RX,
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+ .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
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+ },
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+};
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+
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+static struct sh_dmae_pdata usb_dma_platform_data = {
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+ .slave = r8a7740_usb_dma_slaves,
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+ .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
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+ .channel = r8a7740_usb_dma_channels,
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+ .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
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+ .ts_low_shift = USBTS_LOW_SHIFT,
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+ .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
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+ .ts_high_shift = USBTS_HI_SHIFT,
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+ .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
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+ .ts_shift = dma_usbts_shift,
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+ .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
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+ .dmaor_init = DMAOR_DME,
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+ .chcr_offset = 0x14,
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+ .chcr_ie_bit = 1 << 5,
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+ .dmaor_is_32bit = 1,
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+ .needs_tend_set = 1,
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+ .no_dmars = 1,
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+ .slave_only = 1,
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+};
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+
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+static struct resource r8a7740_usb_dma_resources[] = {
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+ {
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+ /* Channel registers and DMAOR */
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+ .start = 0xe68a0020,
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+ .end = 0xe68a0064 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ /* VCR/SWR/DMICR */
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+ .start = 0xe68a0000,
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+ .end = 0xe68a0014 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ /* IRQ for channels */
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+ .start = evt2irq(0x0a00),
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+ .end = evt2irq(0x0a00),
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct platform_device usb_dma_device = {
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+ .name = "sh-dma-engine",
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+ .id = 3,
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+ .resource = r8a7740_usb_dma_resources,
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+ .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
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+ .dev = {
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+ .platform_data = &usb_dma_platform_data,
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+ },
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+};
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+
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/* I2C */
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static struct resource i2c0_resources[] = {
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[0] = {
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@@ -322,6 +593,10 @@ static struct platform_device i2c1_device = {
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static struct platform_device *r8a7740_late_devices[] __initdata = {
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&i2c0_device,
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&i2c1_device,
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+ &dma0_device,
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+ &dma1_device,
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+ &dma2_device,
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+ &usb_dma_device,
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};
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/*
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@@ -398,10 +673,31 @@ void __init r8a7740_add_standard_devices(void)
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r8a7740_i2c_workaround(&i2c0_device);
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r8a7740_i2c_workaround(&i2c1_device);
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+ /* PM domain */
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+ rmobile_init_pm_domain(&r8a7740_pd_a4s);
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+ rmobile_init_pm_domain(&r8a7740_pd_a3sp);
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+ rmobile_init_pm_domain(&r8a7740_pd_a4lc);
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+
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+ rmobile_pm_add_subdomain(&r8a7740_pd_a4s, &r8a7740_pd_a3sp);
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+
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+ /* add devices */
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platform_add_devices(r8a7740_early_devices,
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ARRAY_SIZE(r8a7740_early_devices));
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platform_add_devices(r8a7740_late_devices,
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ARRAY_SIZE(r8a7740_late_devices));
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+
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+ /* add devices to PM domain */
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+
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+ rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif0_device);
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+ rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif1_device);
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+ rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif2_device);
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+ rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif3_device);
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+ rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif4_device);
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+ rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif5_device);
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+ rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif6_device);
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+ rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif7_device);
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+ rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scifb_device);
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+ rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &i2c1_device);
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}
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static void __init r8a7740_earlytimer_init(void)
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@@ -421,3 +717,49 @@ void __init r8a7740_add_early_devices(void)
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/* override timer setup with soc-specific code */
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shmobile_timer.init = r8a7740_earlytimer_init;
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}
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+
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+#ifdef CONFIG_USE_OF
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+
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+void __init r8a7740_add_early_devices_dt(void)
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+{
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+ shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
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+
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+ early_platform_add_devices(r8a7740_early_devices,
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+ ARRAY_SIZE(r8a7740_early_devices));
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+
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+ /* setup early console here as well */
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+ shmobile_setup_console();
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+}
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+
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+static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
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+ { }
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+};
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+
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+void __init r8a7740_add_standard_devices_dt(void)
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+{
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+ /* clocks are setup late during boot in the case of DT */
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+ r8a7740_clock_init(0);
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+
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+ platform_add_devices(r8a7740_early_devices,
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+ ARRAY_SIZE(r8a7740_early_devices));
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+
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+ of_platform_populate(NULL, of_default_bus_match_table,
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+ r8a7740_auxdata_lookup, NULL);
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+}
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+
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+static const char *r8a7740_boards_compat_dt[] __initdata = {
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+ "renesas,r8a7740",
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+ NULL,
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+};
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+
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+DT_MACHINE_START(SH7372_DT, "Generic R8A7740 (Flattened Device Tree)")
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+ .map_io = r8a7740_map_io,
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+ .init_early = r8a7740_add_early_devices_dt,
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+ .init_irq = r8a7740_init_irq,
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+ .handle_irq = shmobile_handle_irq_intc,
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+ .init_machine = r8a7740_add_standard_devices_dt,
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+ .timer = &shmobile_timer,
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+ .dt_compat = r8a7740_boards_compat_dt,
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+MACHINE_END
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+
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+#endif /* CONFIG_USE_OF */
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Rafael J. Wysocki