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@@ -881,6 +881,74 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
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return ret;
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}
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+static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
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+{
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+ int err;
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+
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+ err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
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+ if (err)
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+ goto done;
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+
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+ err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
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+ if (err)
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+ goto done;
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+
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+ err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
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+ MII_TG3_MMD_CTRL_DATA_NOINC | devad);
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+ if (err)
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+ goto done;
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+
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+ err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
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+
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+done:
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+ return err;
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+}
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+
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+static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
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+{
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+ int err;
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+
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+ err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
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+ if (err)
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+ goto done;
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+
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+ err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
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+ if (err)
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+ goto done;
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+
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+ err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
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+ MII_TG3_MMD_CTRL_DATA_NOINC | devad);
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+ if (err)
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+ goto done;
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+
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+ err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
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+
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+done:
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+ return err;
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+}
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+
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+static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
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+{
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+ int err;
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+
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+ err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
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+ if (!err)
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+ err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
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+
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+ return err;
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+}
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+
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+static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
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+{
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+ int err;
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+
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+ err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
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+ if (!err)
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+ err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
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+
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+ return err;
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+}
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+
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static int tg3_bmcr_reset(struct tg3 *tp)
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{
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u32 phy_control;
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@@ -1154,52 +1222,6 @@ static void tg3_mdio_fini(struct tg3 *tp)
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}
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}
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-static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
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-{
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- int err;
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-
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- err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
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- if (err)
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- goto done;
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-
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- err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
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- if (err)
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- goto done;
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-
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- err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
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- MII_TG3_MMD_CTRL_DATA_NOINC | devad);
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- if (err)
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- goto done;
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-
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- err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
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-
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-done:
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- return err;
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-}
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-
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-static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
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-{
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- int err;
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-
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- err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
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- if (err)
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- goto done;
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-
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- err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
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- if (err)
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- goto done;
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-
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- err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
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- MII_TG3_MMD_CTRL_DATA_NOINC | devad);
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- if (err)
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- goto done;
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-
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- err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
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-
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-done:
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- return err;
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-}
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-
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/* tp->lock is held. */
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static inline void tg3_generate_fw_event(struct tg3 *tp)
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{
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@@ -1576,28 +1598,6 @@ static void tg3_phy_fini(struct tg3 *tp)
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}
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}
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-static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
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-{
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- int err;
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-
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- err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
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- if (!err)
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- err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
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-
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- return err;
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-}
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-
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-static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
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-{
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- int err;
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-
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- err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
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- if (!err)
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- err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
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-
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- return err;
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-}
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-
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static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
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{
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u32 phytest;
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