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@@ -26,7 +26,6 @@
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#include <asm/proto.h>
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#include <asm/kdebug.h>
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#include <asm/mce.h>
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-#include <asm/intel_arch_perfmon.h>
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/*
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* lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
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@@ -66,9 +65,6 @@ static unsigned int nmi_p4_cccr_val;
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#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
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#define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
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-#define ARCH_PERFMON_NMI_EVENT_SEL ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
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-#define ARCH_PERFMON_NMI_EVENT_UMASK ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
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-
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#define MSR_P4_MISC_ENABLE 0x1A0
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#define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
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#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
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@@ -100,10 +96,7 @@ static __cpuinit inline int nmi_known_cpu(void)
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case X86_VENDOR_AMD:
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return boot_cpu_data.x86 == 15;
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case X86_VENDOR_INTEL:
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- if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
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- return 1;
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- else
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- return (boot_cpu_data.x86 == 15);
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+ return boot_cpu_data.x86 == 15;
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}
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return 0;
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}
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@@ -209,8 +202,6 @@ int __init setup_nmi_watchdog(char *str)
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__setup("nmi_watchdog=", setup_nmi_watchdog);
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-static void disable_intel_arch_watchdog(void);
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-
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static void disable_lapic_nmi_watchdog(void)
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{
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if (nmi_active <= 0)
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@@ -223,8 +214,6 @@ static void disable_lapic_nmi_watchdog(void)
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if (boot_cpu_data.x86 == 15) {
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wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
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wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
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- } else if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
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- disable_intel_arch_watchdog();
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}
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break;
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}
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@@ -377,53 +366,6 @@ static void setup_k7_watchdog(void)
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wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
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}
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-static void disable_intel_arch_watchdog(void)
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-{
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- unsigned ebx;
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-
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- /*
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- * Check whether the Architectural PerfMon supports
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- * Unhalted Core Cycles Event or not.
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- * NOTE: Corresponding bit = 0 in ebp indicates event present.
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- */
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- ebx = cpuid_ebx(10);
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- if (!(ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
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- wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, 0, 0);
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-}
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-
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-static int setup_intel_arch_watchdog(void)
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-{
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- unsigned int evntsel;
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- unsigned ebx;
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-
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- /*
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- * Check whether the Architectural PerfMon supports
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- * Unhalted Core Cycles Event or not.
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- * NOTE: Corresponding bit = 0 in ebp indicates event present.
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- */
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- ebx = cpuid_ebx(10);
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- if ((ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
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- return 0;
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-
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- nmi_perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
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-
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- clear_msr_range(MSR_ARCH_PERFMON_EVENTSEL0, 2);
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- clear_msr_range(MSR_ARCH_PERFMON_PERFCTR0, 2);
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-
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- evntsel = ARCH_PERFMON_EVENTSEL_INT
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- | ARCH_PERFMON_EVENTSEL_OS
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- | ARCH_PERFMON_EVENTSEL_USR
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- | ARCH_PERFMON_NMI_EVENT_SEL
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- | ARCH_PERFMON_NMI_EVENT_UMASK;
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-
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- wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);
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- wrmsrl(MSR_ARCH_PERFMON_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));
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- apic_write(APIC_LVTPC, APIC_DM_NMI);
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- evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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- wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);
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- return 1;
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-}
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-
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static int setup_p4_watchdog(void)
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{
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@@ -477,16 +419,10 @@ void setup_apic_nmi_watchdog(void)
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setup_k7_watchdog();
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break;
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case X86_VENDOR_INTEL:
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- if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
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- if (!setup_intel_arch_watchdog())
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- return;
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- } else if (boot_cpu_data.x86 == 15) {
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- if (!setup_p4_watchdog())
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- return;
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- } else {
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+ if (boot_cpu_data.x86 != 15)
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+ return;
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+ if (!setup_p4_watchdog())
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return;
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- }
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-
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break;
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default:
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@@ -571,14 +507,7 @@ void __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
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*/
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wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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- } else if (nmi_perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
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- /*
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- * For Intel based architectural perfmon
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- * - LVTPC is masked on interrupt and must be
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- * unmasked by the LVTPC handler.
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- */
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- apic_write(APIC_LVTPC, APIC_DM_NMI);
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- }
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+ }
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wrmsrl(nmi_perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
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}
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}
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Andi Kleen