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@@ -52,11 +52,11 @@
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#define AT91_MB_RX_FIRST 1
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#define AT91_MB_RX_FIRST 1
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#define AT91_MB_RX_LAST 11
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#define AT91_MB_RX_LAST 11
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-#define AT91_MB_RX_MASK(i) ((1 << (i)) - 1)
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+#define AT91_MB_MASK(i) ((1 << (i)) - 1)
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#define AT91_MB_RX_SPLIT 8
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#define AT91_MB_RX_SPLIT 8
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#define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1)
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#define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1)
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-#define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT) & \
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- ~AT91_MB_RX_MASK(AT91_MB_RX_FIRST))
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+#define AT91_MB_RX_LOW_MASK (AT91_MB_MASK(AT91_MB_RX_SPLIT) & \
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+ ~AT91_MB_MASK(AT91_MB_RX_FIRST))
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#define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT)
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#define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT)
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#define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1)
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#define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1)
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@@ -64,7 +64,7 @@
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#define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT)
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#define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT)
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#define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT)
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#define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT)
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-#define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1)
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+#define AT91_NEXT_MB_MASK (AT91_MB_MASK(AT91_MB_TX_SHIFT))
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#define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
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#define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
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/* Common registers */
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/* Common registers */
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@@ -127,10 +127,10 @@ enum at91_mb_mode {
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};
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};
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/* Interrupt mask bits */
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/* Interrupt mask bits */
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-#define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \
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- - (1 << AT91_MB_RX_FIRST))
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-#define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \
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- - (1 << AT91_MB_TX_FIRST))
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+#define AT91_IRQ_MB_RX (AT91_MB_MASK(AT91_MB_RX_LAST + 1) & \
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+ ~AT91_MB_MASK(AT91_MB_RX_FIRST))
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+#define AT91_IRQ_MB_TX (AT91_MB_MASK(AT91_MB_TX_LAST + 1) & \
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+ ~AT91_MB_MASK(AT91_MB_TX_FIRST))
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#define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
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#define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
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#define AT91_IRQ_ERRA (1 << 16)
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#define AT91_IRQ_ERRA (1 << 16)
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@@ -735,7 +735,7 @@ static int at91_poll(struct napi_struct *napi, int quota)
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if (work_done < quota) {
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if (work_done < quota) {
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/* enable IRQs for frame errors and all mailboxes >= rx_next */
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/* enable IRQs for frame errors and all mailboxes >= rx_next */
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u32 reg_ier = AT91_IRQ_ERR_FRAME;
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u32 reg_ier = AT91_IRQ_ERR_FRAME;
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- reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next);
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+ reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_MASK(priv->rx_next);
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napi_complete(napi);
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napi_complete(napi);
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at91_write(priv, AT91_IER, reg_ier);
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at91_write(priv, AT91_IER, reg_ier);
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