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@@ -249,6 +249,8 @@
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#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */
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#define LPCR_RMLS_SH (63-37)
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#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */
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+#define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */
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+#define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */
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#define LPCR_PECE 0x00007000 /* powersave exit cause enable */
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#define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */
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#define LPCR_PECE1 0x00002000 /* decrementer can cause exit */
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