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+/*
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+ * Allwinner A1X SoCs IRQ chip driver.
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+ *
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+ * Copyright (C) 2012 Maxime Ripard
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+ *
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+ * Maxime Ripard <maxime.ripard@free-electrons.com>
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+ *
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+ * Based on code from
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+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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+ * Benn Huang <benn@allwinnertech.com>
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+#include <linux/io.h>
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+#include <linux/irq.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/of_irq.h>
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+
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+#include <linux/irqchip/sunxi.h>
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+
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+#define SUNXI_IRQ_VECTOR_REG 0x00
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+#define SUNXI_IRQ_PROTECTION_REG 0x08
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+#define SUNXI_IRQ_NMI_CTRL_REG 0x0c
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+#define SUNXI_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
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+#define SUNXI_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
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+#define SUNXI_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
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+#define SUNXI_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
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+
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+static void __iomem *sunxi_irq_base;
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+static struct irq_domain *sunxi_irq_domain;
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+
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+void sunxi_irq_ack(struct irq_data *irqd)
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+{
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+ unsigned int irq = irqd_to_hwirq(irqd);
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+ unsigned int irq_off = irq % 32;
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+ int reg = irq / 32;
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+ u32 val;
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+
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+ val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
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+ writel(val | (1 << irq_off),
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+ sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
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+}
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+
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+static void sunxi_irq_mask(struct irq_data *irqd)
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+{
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+ unsigned int irq = irqd_to_hwirq(irqd);
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+ unsigned int irq_off = irq % 32;
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+ int reg = irq / 32;
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+ u32 val;
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+
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+ val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
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+ writel(val & ~(1 << irq_off),
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+ sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
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+}
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+
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+static void sunxi_irq_unmask(struct irq_data *irqd)
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+{
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+ unsigned int irq = irqd_to_hwirq(irqd);
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+ unsigned int irq_off = irq % 32;
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+ int reg = irq / 32;
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+ u32 val;
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+
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+ val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
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+ writel(val | (1 << irq_off),
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+ sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
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+}
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+
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+static struct irq_chip sunxi_irq_chip = {
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+ .name = "sunxi_irq",
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+ .irq_ack = sunxi_irq_ack,
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+ .irq_mask = sunxi_irq_mask,
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+ .irq_unmask = sunxi_irq_unmask,
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+};
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+
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+static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
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+ irq_hw_number_t hw)
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+{
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+ irq_set_chip_and_handler(virq, &sunxi_irq_chip,
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+ handle_level_irq);
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+ set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
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+
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+ return 0;
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+}
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+
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+static struct irq_domain_ops sunxi_irq_ops = {
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+ .map = sunxi_irq_map,
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+ .xlate = irq_domain_xlate_onecell,
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+};
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+
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+static int __init sunxi_of_init(struct device_node *node,
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+ struct device_node *parent)
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+{
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+ sunxi_irq_base = of_iomap(node, 0);
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+ if (!sunxi_irq_base)
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+ panic("%s: unable to map IC registers\n",
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+ node->full_name);
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+
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+ /* Disable all interrupts */
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+ writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
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+ writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
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+ writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
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+
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+ /* Mask all the interrupts */
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+ writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
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+ writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
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+ writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));
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+
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+ /* Clear all the pending interrupts */
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+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
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+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
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+ writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
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+
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+ /* Enable protection mode */
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+ writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
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+
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+ /* Configure the external interrupt source type */
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+ writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
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+
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+ sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
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+ &sunxi_irq_ops, NULL);
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+ if (!sunxi_irq_domain)
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+ panic("%s: unable to create IRQ domain\n", node->full_name);
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+
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+ return 0;
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+}
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+
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+static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
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+ { .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init }
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+};
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+
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+void __init sunxi_init_irq(void)
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+{
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+ of_irq_init(sunxi_irq_dt_ids);
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+}
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+
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+asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
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+{
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+ u32 irq, hwirq;
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+
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+ hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
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+ while (hwirq != 0) {
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+ irq = irq_find_mapping(sunxi_irq_domain, hwirq);
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+ handle_IRQ(irq, regs);
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+ hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
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+ }
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+}
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Maxime Ripard