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@@ -136,6 +136,14 @@ void mal_enable_rx_channel(struct mal_instance *mal, int channel)
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{
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unsigned long flags;
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+ /*
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+ * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple
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+ * of 8, but enabling in MAL_RXCASR needs the divided by 8 value
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+ * for the bitmask
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+ */
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+ if (!(channel % 8))
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+ channel >>= 3;
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+
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spin_lock_irqsave(&mal->lock, flags);
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MAL_DBG(mal, "enable_rx(%d)" NL, channel);
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@@ -148,6 +156,14 @@ void mal_enable_rx_channel(struct mal_instance *mal, int channel)
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void mal_disable_rx_channel(struct mal_instance *mal, int channel)
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{
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+ /*
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+ * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple
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+ * of 8, but enabling in MAL_RXCASR needs the divided by 8 value
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+ * for the bitmask
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+ */
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+ if (!(channel % 8))
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+ channel >>= 3;
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+
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set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
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MAL_DBG(mal, "disable_rx(%d)" NL, channel);
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