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@@ -1908,12 +1908,23 @@ void sci_controller_power_control_queue_remove(struct isci_host *ihost,
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ihost->power_control.requesters[iphy->phy_index] = NULL;
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}
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+static int is_long_cable(int phy, unsigned char selection_byte)
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+{
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+ return 0;
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+}
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+
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+static int is_medium_cable(int phy, unsigned char selection_byte)
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+{
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+ return 0;
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+}
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+
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#define AFE_REGISTER_WRITE_DELAY 10
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static void sci_controller_afe_initialization(struct isci_host *ihost)
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{
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struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
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const struct sci_oem_params *oem = &ihost->oem_parameters;
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+ unsigned char cable_selection_mask = 0;
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struct pci_dev *pdev = ihost->pdev;
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u32 afe_status;
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u32 phy_id;
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@@ -1922,11 +1933,11 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
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writel(0x0081000f, &afe->afe_dfx_master_control0);
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udelay(AFE_REGISTER_WRITE_DELAY);
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- if (is_b0(pdev)) {
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+ if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) {
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/* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
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* Timer, PM Stagger Timer
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*/
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- writel(0x0007BFFF, &afe->afe_pmsn_master_control2);
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+ writel(0x0007FFFF, &afe->afe_pmsn_master_control2);
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udelay(AFE_REGISTER_WRITE_DELAY);
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}
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@@ -1935,14 +1946,23 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
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writel(0x00005A00, &afe->afe_bias_control);
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else if (is_b0(pdev) || is_c0(pdev))
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writel(0x00005F00, &afe->afe_bias_control);
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+ else if (is_c1(pdev))
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+ writel(0x00005500, &afe->afe_bias_control);
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udelay(AFE_REGISTER_WRITE_DELAY);
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/* Enable PLL */
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- if (is_b0(pdev) || is_c0(pdev))
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- writel(0x80040A08, &afe->afe_pll_control0);
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- else
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+ if (is_a2(pdev))
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writel(0x80040908, &afe->afe_pll_control0);
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+ else if (is_b0(pdev) || is_c0(pdev))
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+ writel(0x80040A08, &afe->afe_pll_control0);
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+ else if (is_c1(pdev)) {
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+ writel(0x80000B08, &afe->afe_pll_control0);
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+ udelay(AFE_REGISTER_WRITE_DELAY);
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+ writel(0x00000B08, &afe->afe_pll_control0);
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+ udelay(AFE_REGISTER_WRITE_DELAY);
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+ writel(0x80000B08, &afe->afe_pll_control0);
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+ }
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udelay(AFE_REGISTER_WRITE_DELAY);
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@@ -1963,46 +1983,68 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
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for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
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struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_id];
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const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
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+ int cable_length_long =
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+ is_long_cable(phy_id, cable_selection_mask);
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+ int cable_length_medium =
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+ is_medium_cable(phy_id, cable_selection_mask);
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+
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+ if (is_a2(pdev)) {
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+ /* All defaults, except the Receive Word
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+ * Alignament/Comma Detect Enable....(0xe800)
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+ */
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+ writel(0x00004512, &xcvr->afe_xcvr_control0);
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+ udelay(AFE_REGISTER_WRITE_DELAY);
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- if (is_b0(pdev)) {
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- /* Configure transmitter SSC parameters */
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+ writel(0x0050100F, &xcvr->afe_xcvr_control1);
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+ udelay(AFE_REGISTER_WRITE_DELAY);
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+ } else if (is_b0(pdev)) {
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+ /* Configure transmitter SSC parameters */
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writel(0x00030000, &xcvr->afe_tx_ssc_control);
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udelay(AFE_REGISTER_WRITE_DELAY);
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} else if (is_c0(pdev)) {
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- /* Configure transmitter SSC parameters */
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- writel(0x0003000, &xcvr->afe_tx_ssc_control);
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+ /* Configure transmitter SSC parameters */
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+ writel(0x00010202, &xcvr->afe_tx_ssc_control);
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udelay(AFE_REGISTER_WRITE_DELAY);
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/* All defaults, except the Receive Word
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* Alignament/Comma Detect Enable....(0xe800)
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*/
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- writel(0x00004500, &xcvr->afe_xcvr_control0);
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+ writel(0x00014500, &xcvr->afe_xcvr_control0);
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udelay(AFE_REGISTER_WRITE_DELAY);
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- } else {
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+ } else if (is_c1(pdev)) {
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+ /* Configure transmitter SSC parameters */
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+ writel(0x00010202, &xcvr->afe_tx_ssc_control);
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+ udelay(AFE_REGISTER_WRITE_DELAY);
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+
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/* All defaults, except the Receive Word
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* Alignament/Comma Detect Enable....(0xe800)
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*/
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- writel(0x00004512, &xcvr->afe_xcvr_control0);
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- udelay(AFE_REGISTER_WRITE_DELAY);
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-
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- writel(0x0050100F, &xcvr->afe_xcvr_control1);
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+ writel(0x0001C500, &xcvr->afe_xcvr_control0);
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udelay(AFE_REGISTER_WRITE_DELAY);
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}
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- /* Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
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- * & increase TX int & ext bias 20%....(0xe85c)
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+ /* Power up TX and RX out from power down (PWRDNTX and
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+ * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c)
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*/
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if (is_a2(pdev))
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writel(0x000003F0, &xcvr->afe_channel_control);
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else if (is_b0(pdev)) {
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- /* Power down TX and RX (PWRDNTX and PWRDNRX) */
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writel(0x000003D7, &xcvr->afe_channel_control);
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udelay(AFE_REGISTER_WRITE_DELAY);
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+
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writel(0x000003D4, &xcvr->afe_channel_control);
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- } else {
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+ } else if (is_c0(pdev)) {
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writel(0x000001E7, &xcvr->afe_channel_control);
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udelay(AFE_REGISTER_WRITE_DELAY);
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+
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writel(0x000001E4, &xcvr->afe_channel_control);
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+ } else if (is_c1(pdev)) {
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+ writel(cable_length_long ? 0x000002F7 : 0x000001F7,
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+ &xcvr->afe_channel_control);
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+ udelay(AFE_REGISTER_WRITE_DELAY);
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+
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+ writel(cable_length_long ? 0x000002F4 : 0x000001F4,
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+ &xcvr->afe_channel_control);
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}
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udelay(AFE_REGISTER_WRITE_DELAY);
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@@ -2012,7 +2054,16 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
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udelay(AFE_REGISTER_WRITE_DELAY);
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}
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- writel(0x00004100, &xcvr->afe_xcvr_control0);
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+ if (is_a2(pdev) || is_b0(pdev))
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+ /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0,
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+ * TPD=0x0(TX Power On), RDD=0x0(RX Detect
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+ * Enabled) ....(0xe800)
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+ */
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+ writel(0x00004100, &xcvr->afe_xcvr_control0);
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+ else if (is_c0(pdev))
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+ writel(0x00014100, &xcvr->afe_xcvr_control0);
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+ else if (is_c1(pdev))
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+ writel(0x0001C100, &xcvr->afe_xcvr_control0);
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udelay(AFE_REGISTER_WRITE_DELAY);
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/* Leave DFE/FFE on */
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@@ -2023,13 +2074,29 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
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udelay(AFE_REGISTER_WRITE_DELAY);
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/* Enable TX equalization (0xe824) */
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writel(0x00040000, &xcvr->afe_tx_control);
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- } else {
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- writel(0x0140DF0F, &xcvr->afe_rx_ssc_control1);
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+ } else if (is_c0(pdev)) {
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+ writel(0x01400C0F, &xcvr->afe_rx_ssc_control1);
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udelay(AFE_REGISTER_WRITE_DELAY);
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writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0);
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udelay(AFE_REGISTER_WRITE_DELAY);
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+ /* Enable TX equalization (0xe824) */
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+ writel(0x00040000, &xcvr->afe_tx_control);
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+ } else if (is_c1(pdev)) {
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+ writel(cable_length_long ? 0x01500C0C :
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+ cable_length_medium ? 0x01400C0D : 0x02400C0D,
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+ &xcvr->afe_xcvr_control1);
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+ udelay(AFE_REGISTER_WRITE_DELAY);
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+
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+ writel(0x000003E0, &xcvr->afe_dfx_rx_control1);
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+ udelay(AFE_REGISTER_WRITE_DELAY);
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+
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+ writel(cable_length_long ? 0x33091C1F :
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+ cable_length_medium ? 0x3315181F : 0x2B17161F,
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+ &xcvr->afe_rx_ssc_control0);
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+ udelay(AFE_REGISTER_WRITE_DELAY);
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+
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/* Enable TX equalization (0xe824) */
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writel(0x00040000, &xcvr->afe_tx_control);
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}
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