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@@ -481,34 +481,22 @@ typedef struct asc_risc_sg_list_q {
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#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
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#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
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#define ASC_MAX_INRAM_TAG_QNG 16
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#define ASC_MAX_INRAM_TAG_QNG 16
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#define ASC_IOADR_GAP 0x10
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#define ASC_IOADR_GAP 0x10
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-#define ASC_MAX_SYN_XFER_NO 16
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#define ASC_SYN_MAX_OFFSET 0x0F
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#define ASC_SYN_MAX_OFFSET 0x0F
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#define ASC_DEF_SDTR_OFFSET 0x0F
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#define ASC_DEF_SDTR_OFFSET 0x0F
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#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
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#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
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-#define SYN_XFER_NS_0 25
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-#define SYN_XFER_NS_1 30
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-#define SYN_XFER_NS_2 35
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-#define SYN_XFER_NS_3 40
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-#define SYN_XFER_NS_4 50
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-#define SYN_XFER_NS_5 60
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-#define SYN_XFER_NS_6 70
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-#define SYN_XFER_NS_7 85
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-#define SYN_ULTRA_XFER_NS_0 12
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-#define SYN_ULTRA_XFER_NS_1 19
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-#define SYN_ULTRA_XFER_NS_2 25
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-#define SYN_ULTRA_XFER_NS_3 32
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-#define SYN_ULTRA_XFER_NS_4 38
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-#define SYN_ULTRA_XFER_NS_5 44
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-#define SYN_ULTRA_XFER_NS_6 50
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-#define SYN_ULTRA_XFER_NS_7 57
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-#define SYN_ULTRA_XFER_NS_8 63
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-#define SYN_ULTRA_XFER_NS_9 69
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-#define SYN_ULTRA_XFER_NS_10 75
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-#define SYN_ULTRA_XFER_NS_11 82
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-#define SYN_ULTRA_XFER_NS_12 88
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-#define SYN_ULTRA_XFER_NS_13 94
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-#define SYN_ULTRA_XFER_NS_14 100
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-#define SYN_ULTRA_XFER_NS_15 107
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+#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
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+
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+/* The narrow chip only supports a limited selection of transfer rates.
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+ * These are encoded in the range 0..7 or 0..15 depending whether the chip
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+ * is Ultra-capable or not. These tables let us convert from one to the other.
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+ */
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+static const unsigned char asc_syn_xfer_period[8] = {
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+ 25, 30, 35, 40, 50, 60, 70, 85
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+};
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+
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+static const unsigned char asc_syn_ultra_xfer_period[16] = {
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+ 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
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+};
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typedef struct ext_msg {
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typedef struct ext_msg {
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uchar msg_type;
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uchar msg_type;
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@@ -572,7 +560,6 @@ typedef struct asc_dvc_cfg {
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#define ASC_INIT_STATE_WITHOUT_EEP 0x8000
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#define ASC_INIT_STATE_WITHOUT_EEP 0x8000
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#define ASC_BUG_FIX_IF_NOT_DWB 0x0001
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#define ASC_BUG_FIX_IF_NOT_DWB 0x0001
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#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
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#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
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-#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
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#define ASC_MIN_TAGGED_CMD 7
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#define ASC_MIN_TAGGED_CMD 7
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#define ASC_MAX_SCSI_RESET_WAIT 30
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#define ASC_MAX_SCSI_RESET_WAIT 30
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@@ -602,7 +589,7 @@ typedef struct asc_dvc_var {
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uchar max_dvc_qng[ASC_MAX_TID + 1];
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uchar max_dvc_qng[ASC_MAX_TID + 1];
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ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
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ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
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ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
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ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
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- uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
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+ const uchar *sdtr_period_tbl;
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ASC_DVC_CFG *cfg;
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ASC_DVC_CFG *cfg;
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ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
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ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
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char redo_scam;
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char redo_scam;
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@@ -611,8 +598,8 @@ typedef struct asc_dvc_var {
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ASC_DCNT max_dma_count;
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ASC_DCNT max_dma_count;
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ASC_SCSI_BIT_ID_TYPE no_scam;
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ASC_SCSI_BIT_ID_TYPE no_scam;
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ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
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ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
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+ uchar min_sdtr_index;
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uchar max_sdtr_index;
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uchar max_sdtr_index;
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- uchar host_init_sdtr_index;
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struct asc_board *drv_ptr;
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struct asc_board *drv_ptr;
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ASC_DCNT uc_break;
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ASC_DCNT uc_break;
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} ASC_DVC_VAR;
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} ASC_DVC_VAR;
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@@ -896,7 +883,6 @@ typedef struct asc_mc_saved {
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#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
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#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
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#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
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#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
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#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
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#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
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-#define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
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#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
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#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
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#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
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#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
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#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
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#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
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@@ -8556,14 +8542,14 @@ static void AscAckInterrupt(PortAddr iop_base)
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static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
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static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
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{
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{
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- uchar *period_table;
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+ const uchar *period_table;
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int max_index;
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int max_index;
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int min_index;
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int min_index;
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int i;
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int i;
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period_table = asc_dvc->sdtr_period_tbl;
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period_table = asc_dvc->sdtr_period_tbl;
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max_index = (int)asc_dvc->max_sdtr_index;
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max_index = (int)asc_dvc->max_sdtr_index;
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- min_index = (int)asc_dvc->host_init_sdtr_index;
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+ min_index = (int)asc_dvc->min_sdtr_index;
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if ((syn_time <= period_table[max_index])) {
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if ((syn_time <= period_table[max_index])) {
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for (i = min_index; i < (max_index - 1); i++) {
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for (i = min_index; i < (max_index - 1); i++) {
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if (syn_time <= period_table[i]) {
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if (syn_time <= period_table[i]) {
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@@ -8612,9 +8598,8 @@ AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
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uchar sdtr_period_ix;
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uchar sdtr_period_ix;
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sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
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sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
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- if (sdtr_period_ix > asc_dvc->max_sdtr_index) {
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+ if (sdtr_period_ix > asc_dvc->max_sdtr_index)
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return 0xFF;
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return 0xFF;
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- }
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byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
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byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
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return byte;
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return byte;
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}
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}
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@@ -8725,15 +8710,14 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
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ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
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ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
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}
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}
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if ((ext_msg.xfer_period <
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if ((ext_msg.xfer_period <
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- asc_dvc->sdtr_period_tbl[asc_dvc->
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- host_init_sdtr_index])
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+ asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
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|| (ext_msg.xfer_period >
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|| (ext_msg.xfer_period >
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asc_dvc->sdtr_period_tbl[asc_dvc->
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asc_dvc->sdtr_period_tbl[asc_dvc->
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max_sdtr_index])) {
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max_sdtr_index])) {
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sdtr_accept = FALSE;
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sdtr_accept = FALSE;
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ext_msg.xfer_period =
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ext_msg.xfer_period =
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asc_dvc->sdtr_period_tbl[asc_dvc->
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asc_dvc->sdtr_period_tbl[asc_dvc->
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- host_init_sdtr_index];
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+ min_sdtr_index];
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}
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}
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if (sdtr_accept) {
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if (sdtr_accept) {
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sdtr_data =
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sdtr_data =
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@@ -8757,7 +8741,6 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
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AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
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AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
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} else {
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} else {
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if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
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if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
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-
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q_cntl &= ~QC_MSG_OUT;
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q_cntl &= ~QC_MSG_OUT;
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asc_dvc->sdtr_done |= target_id;
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asc_dvc->sdtr_done |= target_id;
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asc_dvc->init_sdtr |= target_id;
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asc_dvc->init_sdtr |= target_id;
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@@ -8772,7 +8755,6 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
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tid_no);
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tid_no);
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boardp->sdtr_data[tid_no] = sdtr_data;
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boardp->sdtr_data[tid_no] = sdtr_data;
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} else {
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} else {
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-
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q_cntl |= QC_MSG_OUT;
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q_cntl |= QC_MSG_OUT;
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AscMsgOutSDTR(asc_dvc,
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AscMsgOutSDTR(asc_dvc,
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ext_msg.xfer_period,
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ext_msg.xfer_period,
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@@ -11407,7 +11389,7 @@ static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
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asc_dvc->queue_full_or_busy = 0;
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asc_dvc->queue_full_or_busy = 0;
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asc_dvc->redo_scam = 0;
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asc_dvc->redo_scam = 0;
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asc_dvc->res2 = 0;
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asc_dvc->res2 = 0;
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- asc_dvc->host_init_sdtr_index = 0;
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+ asc_dvc->min_sdtr_index = 0;
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asc_dvc->cfg->can_tagged_qng = 0;
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asc_dvc->cfg->can_tagged_qng = 0;
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asc_dvc->cfg->cmd_qng_enabled = 0;
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asc_dvc->cfg->cmd_qng_enabled = 0;
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asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
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asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
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@@ -11421,34 +11403,12 @@ static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
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asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
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asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
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chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
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chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
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asc_dvc->cfg->chip_version = chip_version;
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asc_dvc->cfg->chip_version = chip_version;
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- asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
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- asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
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- asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
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- asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
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- asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
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- asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
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- asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
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- asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
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+ asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
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asc_dvc->max_sdtr_index = 7;
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asc_dvc->max_sdtr_index = 7;
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if ((asc_dvc->bus_type & ASC_IS_PCI) &&
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if ((asc_dvc->bus_type & ASC_IS_PCI) &&
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(chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
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(chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
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asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
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asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
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- asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
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- asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
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- asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
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- asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
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- asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
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- asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
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- asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
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- asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
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- asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
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- asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
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- asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
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- asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
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- asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
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- asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
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- asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
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- asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
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+ asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
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asc_dvc->max_sdtr_index = 15;
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asc_dvc->max_sdtr_index = 15;
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if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
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if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
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AscSetExtraControl(iop_base,
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AscSetExtraControl(iop_base,
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@@ -11889,7 +11849,7 @@ static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
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asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
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asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
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if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
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if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
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!(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
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!(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
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- asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
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+ asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
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}
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}
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for (i = 0; i <= ASC_MAX_TID; i++) {
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for (i = 0; i <= ASC_MAX_TID; i++) {
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@@ -11897,7 +11857,7 @@ static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
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asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
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asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
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asc_dvc->cfg->sdtr_period_offset[i] =
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asc_dvc->cfg->sdtr_period_offset[i] =
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(uchar)(ASC_DEF_SDTR_OFFSET |
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(uchar)(ASC_DEF_SDTR_OFFSET |
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- (asc_dvc->host_init_sdtr_index << 4));
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+ (asc_dvc->min_sdtr_index << 4));
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}
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}
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eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
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eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
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if (write_eep) {
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if (write_eep) {
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