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@@ -0,0 +1,50 @@
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+/*
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+ * arch/arm/include/asm/byteorder.h
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+ *
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+ * ARM Endian-ness. In little endian mode, the data bus is connected such
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+ * that byte accesses appear as:
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+ * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
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+ * and word accesses (data or instruction) appear as:
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+ * d0...d31
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+ *
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+ * When in big endian mode, byte accesses appear as:
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+ * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
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+ * and word accesses (data or instruction) appear as:
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+ * d0...d31
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+ */
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+#ifndef __ASM_ARM_SWAB_H
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+#define __ASM_ARM_SWAB_H
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+
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+#include <linux/compiler.h>
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+#include <asm/types.h>
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+
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+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
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+# define __SWAB_64_THRU_32__
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+#endif
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+
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+static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
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+{
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+ __u32 t;
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+
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+#ifndef __thumb__
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+ if (!__builtin_constant_p(x)) {
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+ /*
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+ * The compiler needs a bit of a hint here to always do the
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+ * right thing and not screw it up to different degrees
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+ * depending on the gcc version.
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+ */
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+ asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x));
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+ } else
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+#endif
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+ t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */
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+
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+ x = (x << 24) | (x >> 8); /* mov r0,r0,ror #8 */
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+ t &= ~0x00FF0000; /* bic r1,r1,#0x00FF0000 */
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+ x ^= (t >> 8); /* eor r0,r0,r1,lsr #8 */
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+
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+ return x;
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+}
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+#define __arch_swab32 __arch_swab32
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+
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+#endif
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+
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