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@@ -0,0 +1,167 @@
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+#include "drmP.h"
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+#include "drm.h"
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+
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+#include "nouveau_drv.h"
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+#include <engine/fifo.h>
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+#include <core/ramht.h>
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+
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+/* returns the size of fifo context */
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+static int
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+nouveau_fifo_ctx_size(struct drm_device *dev)
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+{
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+ return 128 * 32;
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+}
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+
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+int nv40_instmem_init(struct drm_device *dev)
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+{
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+ struct drm_nouveau_private *dev_priv = dev->dev_private;
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+ struct nouveau_gpuobj *ramht = NULL;
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+ u32 offset, length, vs, rsvd;
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+ int ret;
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+
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+ /* RAMIN always available */
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+ dev_priv->ramin_available = true;
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+
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+ /* Reserve space at end of VRAM for PRAMIN */
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+ /* estimate grctx size, the magics come from nv40_grctx.c */
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+ vs = hweight8((nv_rd32(dev, 0x001540) & 0x0000ff00) >> 8);
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+ if (dev_priv->chipset == 0x40) rsvd = 0x6aa0 * vs;
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+ else if (dev_priv->chipset < 0x43) rsvd = 0x4f00 * vs;
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+ else if (nv44_graph_class(dev)) rsvd = 0x4980 * vs;
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+ else rsvd = 0x4a40 * vs;
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+ rsvd += 16 * 1024;
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+ rsvd *= 32; /* per-channel */
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+
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+ rsvd += 512 * 1024; /* pci(e)gart table */
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+ rsvd += 512 * 1024; /* object storage */
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+
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+ dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096);
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+
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+ /* Setup shared RAMHT */
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+ ret = nouveau_gpuobj_new_fake(dev, 0x10000, ~0, 4096,
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+ NVOBJ_FLAG_ZERO_ALLOC, &ramht);
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+ if (ret)
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+ return ret;
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+
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+ ret = nouveau_ramht_new(dev, ramht, &dev_priv->ramht);
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+ nouveau_gpuobj_ref(NULL, &ramht);
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+ if (ret)
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+ return ret;
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+
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+ /* And RAMRO */
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+ ret = nouveau_gpuobj_new_fake(dev, 0x11200, ~0, 512,
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+ NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ramro);
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+ if (ret)
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+ return ret;
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+
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+ /* And RAMFC */
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+ length = nouveau_fifo_ctx_size(dev);
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+ offset = 0x20000;
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+
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+ ret = nouveau_gpuobj_new_fake(dev, offset, ~0, length,
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+ NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ramfc);
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+ if (ret)
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+ return ret;
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+
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+ /* Only allow space after RAMFC to be used for object allocation */
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+ offset += length;
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+
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+ /* It appears RAMRO (or something?) is controlled by 0x2220/0x2230
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+ * on certain NV4x chipsets as well as RAMFC. When 0x2230 == 0
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+ * ("new style" control) the upper 16-bits of 0x2220 points at this
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+ * other mysterious table that's clobbering important things.
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+ *
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+ * We're now pointing this at RAMIN+0x30000 to avoid RAMFC getting
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+ * smashed to pieces on us, so reserve 0x30000-0x40000 too..
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+ */
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+ if (offset < 0x40000)
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+ offset = 0x40000;
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+
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+ ret = drm_mm_init(&dev_priv->ramin_heap, offset,
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+ dev_priv->ramin_rsvd_vram - offset);
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+ if (ret) {
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+ NV_ERROR(dev, "Failed to init RAMIN heap: %d\n", ret);
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+void
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+nv40_instmem_takedown(struct drm_device *dev)
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+{
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+ struct drm_nouveau_private *dev_priv = dev->dev_private;
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+
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+ nouveau_ramht_ref(NULL, &dev_priv->ramht, NULL);
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+ nouveau_gpuobj_ref(NULL, &dev_priv->ramro);
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+ nouveau_gpuobj_ref(NULL, &dev_priv->ramfc);
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+
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+ if (drm_mm_initialized(&dev_priv->ramin_heap))
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+ drm_mm_takedown(&dev_priv->ramin_heap);
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+}
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+
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+int
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+nv40_instmem_suspend(struct drm_device *dev)
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+{
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+ return 0;
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+}
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+
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+void
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+nv40_instmem_resume(struct drm_device *dev)
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+{
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+}
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+
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+int
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+nv40_instmem_get(struct nouveau_gpuobj *gpuobj, struct nouveau_channel *chan,
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+ u32 size, u32 align)
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+{
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+ struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
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+ struct drm_mm_node *ramin = NULL;
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+
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+ do {
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+ if (drm_mm_pre_get(&dev_priv->ramin_heap))
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+ return -ENOMEM;
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+
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+ spin_lock(&dev_priv->ramin_lock);
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+ ramin = drm_mm_search_free(&dev_priv->ramin_heap, size, align, 0);
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+ if (ramin == NULL) {
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+ spin_unlock(&dev_priv->ramin_lock);
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+ return -ENOMEM;
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+ }
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+
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+ ramin = drm_mm_get_block_atomic(ramin, size, align);
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+ spin_unlock(&dev_priv->ramin_lock);
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+ } while (ramin == NULL);
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+
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+ gpuobj->node = ramin;
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+ gpuobj->vinst = ramin->start;
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+ return 0;
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+}
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+
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+void
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+nv40_instmem_put(struct nouveau_gpuobj *gpuobj)
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+{
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+ struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
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+
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+ spin_lock(&dev_priv->ramin_lock);
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+ drm_mm_put_block(gpuobj->node);
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+ gpuobj->node = NULL;
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+ spin_unlock(&dev_priv->ramin_lock);
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+}
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+
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+int
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+nv40_instmem_map(struct nouveau_gpuobj *gpuobj)
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+{
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+ gpuobj->pinst = gpuobj->vinst;
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+ return 0;
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+}
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+
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+void
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+nv40_instmem_unmap(struct nouveau_gpuobj *gpuobj)
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+{
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+}
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+
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+void
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+nv40_instmem_flush(struct drm_device *dev)
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+{
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+}
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Ben Skeggs