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@@ -74,7 +74,7 @@ struct core99_header {
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* Read and write the non-volatile RAM on PowerMacs and CHRP machines.
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*/
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static int nvram_naddrs;
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-static volatile unsigned char *nvram_data;
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+static volatile unsigned char __iomem *nvram_data;
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static int is_core_99;
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static int core99_bank = 0;
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static int nvram_partitions[3];
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@@ -148,7 +148,7 @@ static ssize_t core99_nvram_size(void)
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}
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#ifdef CONFIG_PPC32
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-static volatile unsigned char *nvram_addr;
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+static volatile unsigned char __iomem *nvram_addr;
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static int nvram_mult;
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static unsigned char direct_nvram_read_byte(int addr)
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@@ -285,7 +285,7 @@ static int sm_erase_bank(int bank)
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int stat, i;
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unsigned long timeout;
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- u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
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+ u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
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@@ -317,7 +317,7 @@ static int sm_write_bank(int bank, u8* datas)
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int i, stat = 0;
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unsigned long timeout;
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- u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
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+ u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
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@@ -352,7 +352,7 @@ static int amd_erase_bank(int bank)
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int i, stat = 0;
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unsigned long timeout;
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- u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
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+ u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: AMD Erasing bank %d...\n", bank);
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@@ -399,7 +399,7 @@ static int amd_write_bank(int bank, u8* datas)
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int i, stat = 0;
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unsigned long timeout;
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- u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
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+ u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: AMD Writing bank %d...\n", bank);
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