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@@ -465,8 +465,8 @@ typedef struct _pcie_enhanced_caphdr {
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#define bar0_window dev_dep[0x80 - 0x40]
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#define bar1_window dev_dep[0x84 - 0x40]
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#define sprom_control dev_dep[0x88 - 0x40]
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-#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
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-#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
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+#define PCI_BAR0_WIN 0x80 /* backplane address space accessed by BAR0 */
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+#define PCI_BAR1_WIN 0x84 /* backplane address space accessed by BAR1 */
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#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
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#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
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#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
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@@ -475,7 +475,7 @@ typedef struct _pcie_enhanced_caphdr {
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#define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */
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#define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */
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#define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */
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-#define PCI_BAR0_WIN2 0xac /* backplane addres space accessed by second 4KB of BAR0 */
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+#define PCI_BAR0_WIN2 0xac /* backplane address space accessed by second 4KB of BAR0 */
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#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
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#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
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#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
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