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@@ -218,8 +218,10 @@ static int imxmci_busy_wait_for_status(struct imxmci_host *host,
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if(!loops)
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return 0;
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- dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
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- loops, where, *pstat, stat_mask);
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+ /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
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+ if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000))
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+ dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
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+ loops, where, *pstat, stat_mask);
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return loops;
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}
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@@ -333,6 +335,9 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
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WARN_ON(host->cmd != NULL);
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host->cmd = cmd;
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+ /* Ensure, that clock are stopped else command programming and start fails */
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+ imxmci_stop_clock(host);
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+
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if (cmd->flags & MMC_RSP_BUSY)
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cmdat |= CMD_DAT_CONT_BUSY;
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@@ -553,7 +558,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
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int trans_done = 0;
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unsigned int stat = *pstat;
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- if(host->actual_bus_width == MMC_BUS_WIDTH_4)
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+ if(host->actual_bus_width != MMC_BUS_WIDTH_4)
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burst_len = 16;
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else
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burst_len = 64;
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@@ -591,8 +596,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
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stat = MMC_STATUS;
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/* Flush extra bytes from FIFO */
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- while(flush_len >= 2){
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- flush_len -= 2;
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+ while(flush_len && !(stat & STATUS_DATA_TRANS_DONE)){
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i = MMC_BUFFER_ACCESS;
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stat = MMC_STATUS;
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stat &= ~STATUS_CRC_READ_ERR; /* Stupid but required there */
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@@ -746,10 +750,6 @@ static void imxmci_tasklet_fnc(unsigned long data)
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data_dir_mask = STATUS_DATA_TRANS_DONE;
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}
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- imxmci_busy_wait_for_status(host, &stat,
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- data_dir_mask,
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- 50, "imxmci_tasklet_fnc data");
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-
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if(stat & data_dir_mask) {
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clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
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imxmci_data_done(host, stat);
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@@ -865,7 +865,11 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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imxmci_stop_clock(host);
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MMC_CLK_RATE = (prescaler<<3) | clk;
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- imxmci_start_clock(host);
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+ /*
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+ * Under my understanding, clock should not be started there, because it would
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+ * initiate SDHC sequencer and send last or random command into card
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+ */
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+ /*imxmci_start_clock(host);*/
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dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
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} else {
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