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@@ -709,6 +709,21 @@ static inline void omap2_enable_irq_lch(int lch)
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spin_unlock_irqrestore(&dma_chan_lock, flags);
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}
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+static inline void omap2_disable_irq_lch(int lch)
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+{
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+ u32 val;
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+ unsigned long flags;
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+
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+ if (!cpu_class_is_omap2())
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+ return;
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+
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+ spin_lock_irqsave(&dma_chan_lock, flags);
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+ val = dma_read(IRQENABLE_L0);
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+ val &= ~(1 << lch);
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+ dma_write(val, IRQENABLE_L0);
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+ spin_unlock_irqrestore(&dma_chan_lock, flags);
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+}
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+
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int omap_request_dma(int dev_id, const char *dev_name,
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void (*callback)(int lch, u16 ch_status, void *data),
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void *data, int *dma_ch_out)
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@@ -807,14 +822,7 @@ void omap_free_dma(int lch)
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}
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if (cpu_class_is_omap2()) {
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- u32 val;
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-
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- spin_lock_irqsave(&dma_chan_lock, flags);
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- /* Disable interrupts */
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- val = dma_read(IRQENABLE_L0);
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- val &= ~(1 << lch);
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- dma_write(val, IRQENABLE_L0);
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- spin_unlock_irqrestore(&dma_chan_lock, flags);
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+ omap2_disable_irq_lch(lch);
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/* Clear the CSR register and IRQ status register */
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dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
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@@ -2107,6 +2115,9 @@ static int __init omap_init_dma(void)
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for (ch = 0; ch < dma_chan_count; ch++) {
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omap_clear_dma(ch);
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+ if (cpu_class_is_omap2())
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+ omap2_disable_irq_lch(ch);
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+
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dma_chan[ch].dev_id = -1;
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dma_chan[ch].next_lch = -1;
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