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@@ -52,6 +52,264 @@
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#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
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#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
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+/* AMD quirk use */
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+#define AB_REG_BAR_LOW 0xe0
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+#define AB_REG_BAR_HIGH 0xe1
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+#define AB_REG_BAR_SB700 0xf0
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+#define AB_INDX(addr) ((addr) + 0x00)
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+#define AB_DATA(addr) ((addr) + 0x04)
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+#define AX_INDXC 0x30
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+#define AX_DATAC 0x34
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+
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+#define NB_PCIE_INDX_ADDR 0xe0
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+#define NB_PCIE_INDX_DATA 0xe4
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+#define PCIE_P_CNTL 0x10040
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+#define BIF_NB 0x10002
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+#define NB_PIF0_PWRDOWN_0 0x01100012
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+#define NB_PIF0_PWRDOWN_1 0x01100013
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+
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+static struct amd_chipset_info {
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+ struct pci_dev *nb_dev;
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+ struct pci_dev *smbus_dev;
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+ int nb_type;
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+ int sb_type;
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+ int isoc_reqs;
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+ int probe_count;
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+ int probe_result;
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+} amd_chipset;
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+
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+static DEFINE_SPINLOCK(amd_lock);
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+
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+int usb_amd_find_chipset_info(void)
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+{
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+ u8 rev = 0;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&amd_lock, flags);
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+
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+ amd_chipset.probe_count++;
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+ /* probe only once */
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+ if (amd_chipset.probe_count > 1) {
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+ spin_unlock_irqrestore(&amd_lock, flags);
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+ return amd_chipset.probe_result;
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+ }
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+
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+ amd_chipset.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
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+ if (amd_chipset.smbus_dev) {
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+ rev = amd_chipset.smbus_dev->revision;
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+ if (rev >= 0x40)
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+ amd_chipset.sb_type = 1;
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+ else if (rev >= 0x30 && rev <= 0x3b)
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+ amd_chipset.sb_type = 3;
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+ } else {
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+ amd_chipset.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
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+ 0x780b, NULL);
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+ if (!amd_chipset.smbus_dev) {
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+ spin_unlock_irqrestore(&amd_lock, flags);
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+ return 0;
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+ }
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+ rev = amd_chipset.smbus_dev->revision;
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+ if (rev >= 0x11 && rev <= 0x18)
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+ amd_chipset.sb_type = 2;
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+ }
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+
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+ if (amd_chipset.sb_type == 0) {
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+ if (amd_chipset.smbus_dev) {
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+ pci_dev_put(amd_chipset.smbus_dev);
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+ amd_chipset.smbus_dev = NULL;
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+ }
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+ spin_unlock_irqrestore(&amd_lock, flags);
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+ return 0;
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+ }
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+
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+ amd_chipset.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
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+ if (amd_chipset.nb_dev) {
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+ amd_chipset.nb_type = 1;
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+ } else {
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+ amd_chipset.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
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+ 0x1510, NULL);
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+ if (amd_chipset.nb_dev) {
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+ amd_chipset.nb_type = 2;
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+ } else {
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+ amd_chipset.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
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+ 0x9600, NULL);
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+ if (amd_chipset.nb_dev)
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+ amd_chipset.nb_type = 3;
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+ }
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+ }
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+
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+ amd_chipset.probe_result = 1;
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+ printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
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+
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+ spin_unlock_irqrestore(&amd_lock, flags);
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+ return amd_chipset.probe_result;
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+}
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+EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
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+
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+/*
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+ * The hardware normally enables the A-link power management feature, which
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+ * lets the system lower the power consumption in idle states.
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+ *
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+ * This USB quirk prevents the link going into that lower power state
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+ * during isochronous transfers.
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+ *
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+ * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
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+ * some AMD platforms may stutter or have breaks occasionally.
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+ */
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+static void usb_amd_quirk_pll(int disable)
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+{
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+ u32 addr, addr_low, addr_high, val;
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+ u32 bit = disable ? 0 : 1;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&amd_lock, flags);
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+
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+ if (disable) {
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+ amd_chipset.isoc_reqs++;
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+ if (amd_chipset.isoc_reqs > 1) {
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+ spin_unlock_irqrestore(&amd_lock, flags);
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+ return;
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+ }
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+ } else {
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+ amd_chipset.isoc_reqs--;
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+ if (amd_chipset.isoc_reqs > 0) {
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+ spin_unlock_irqrestore(&amd_lock, flags);
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+ return;
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+ }
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+ }
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+
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+ if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) {
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+ outb_p(AB_REG_BAR_LOW, 0xcd6);
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+ addr_low = inb_p(0xcd7);
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+ outb_p(AB_REG_BAR_HIGH, 0xcd6);
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+ addr_high = inb_p(0xcd7);
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+ addr = addr_high << 8 | addr_low;
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+
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+ outl_p(0x30, AB_INDX(addr));
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+ outl_p(0x40, AB_DATA(addr));
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+ outl_p(0x34, AB_INDX(addr));
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+ val = inl_p(AB_DATA(addr));
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+ } else if (amd_chipset.sb_type == 3) {
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+ pci_read_config_dword(amd_chipset.smbus_dev,
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+ AB_REG_BAR_SB700, &addr);
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+ outl(AX_INDXC, AB_INDX(addr));
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+ outl(0x40, AB_DATA(addr));
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+ outl(AX_DATAC, AB_INDX(addr));
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+ val = inl(AB_DATA(addr));
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+ } else {
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+ spin_unlock_irqrestore(&amd_lock, flags);
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+ return;
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+ }
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+
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+ if (disable) {
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+ val &= ~0x08;
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+ val |= (1 << 4) | (1 << 9);
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+ } else {
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+ val |= 0x08;
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+ val &= ~((1 << 4) | (1 << 9));
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+ }
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+ outl_p(val, AB_DATA(addr));
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+
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+ if (!amd_chipset.nb_dev) {
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+ spin_unlock_irqrestore(&amd_lock, flags);
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+ return;
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+ }
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+
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+ if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
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+ addr = PCIE_P_CNTL;
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+ pci_write_config_dword(amd_chipset.nb_dev,
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+ NB_PCIE_INDX_ADDR, addr);
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+ pci_read_config_dword(amd_chipset.nb_dev,
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+ NB_PCIE_INDX_DATA, &val);
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+
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+ val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
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+ val |= bit | (bit << 3) | (bit << 12);
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+ val |= ((!bit) << 4) | ((!bit) << 9);
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+ pci_write_config_dword(amd_chipset.nb_dev,
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+ NB_PCIE_INDX_DATA, val);
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+
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+ addr = BIF_NB;
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+ pci_write_config_dword(amd_chipset.nb_dev,
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+ NB_PCIE_INDX_ADDR, addr);
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+ pci_read_config_dword(amd_chipset.nb_dev,
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+ NB_PCIE_INDX_DATA, &val);
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+ val &= ~(1 << 8);
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+ val |= bit << 8;
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+
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+ pci_write_config_dword(amd_chipset.nb_dev,
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+ NB_PCIE_INDX_DATA, val);
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+ } else if (amd_chipset.nb_type == 2) {
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+ addr = NB_PIF0_PWRDOWN_0;
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+ pci_write_config_dword(amd_chipset.nb_dev,
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+ NB_PCIE_INDX_ADDR, addr);
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+ pci_read_config_dword(amd_chipset.nb_dev,
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+ NB_PCIE_INDX_DATA, &val);
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+ if (disable)
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+ val &= ~(0x3f << 7);
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+ else
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+ val |= 0x3f << 7;
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+
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+ pci_write_config_dword(amd_chipset.nb_dev,
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+ NB_PCIE_INDX_DATA, val);
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+
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+ addr = NB_PIF0_PWRDOWN_1;
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+ pci_write_config_dword(amd_chipset.nb_dev,
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+ NB_PCIE_INDX_ADDR, addr);
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+ pci_read_config_dword(amd_chipset.nb_dev,
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+ NB_PCIE_INDX_DATA, &val);
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+ if (disable)
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+ val &= ~(0x3f << 7);
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+ else
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+ val |= 0x3f << 7;
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+
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+ pci_write_config_dword(amd_chipset.nb_dev,
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+ NB_PCIE_INDX_DATA, val);
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+ }
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+
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+ spin_unlock_irqrestore(&amd_lock, flags);
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+ return;
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+}
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+
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+void usb_amd_quirk_pll_disable(void)
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+{
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+ usb_amd_quirk_pll(1);
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+}
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+EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
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+
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+void usb_amd_quirk_pll_enable(void)
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+{
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+ usb_amd_quirk_pll(0);
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+}
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+EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
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+
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+void usb_amd_dev_put(void)
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+{
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&amd_lock, flags);
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+
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+ amd_chipset.probe_count--;
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+ if (amd_chipset.probe_count > 0) {
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+ spin_unlock_irqrestore(&amd_lock, flags);
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+ return;
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+ }
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+
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+ if (amd_chipset.nb_dev) {
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+ pci_dev_put(amd_chipset.nb_dev);
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+ amd_chipset.nb_dev = NULL;
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+ }
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+ if (amd_chipset.smbus_dev) {
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+ pci_dev_put(amd_chipset.smbus_dev);
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+ amd_chipset.smbus_dev = NULL;
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+ }
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+ amd_chipset.nb_type = 0;
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+ amd_chipset.sb_type = 0;
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+ amd_chipset.isoc_reqs = 0;
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+ amd_chipset.probe_result = 0;
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+
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+ spin_unlock_irqrestore(&amd_lock, flags);
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+}
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+EXPORT_SYMBOL_GPL(usb_amd_dev_put);
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/*
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* Make sure the controller is completely inactive, unable to
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Andiry Xu