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@@ -290,6 +290,12 @@
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/* Tegra CPU clock and reset control regs */
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#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
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+#ifdef CONFIG_PM_SLEEP
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+static struct cpu_clk_suspend_context {
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+ u32 clk_csite_src;
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+} tegra114_cpu_clk_sctx;
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+#endif
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+
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static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
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static void __iomem *clk_base;
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@@ -2142,9 +2148,29 @@ static void tegra114_disable_cpu_clock(u32 cpu)
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/* flow controller would take care in the power sequence. */
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}
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+#ifdef CONFIG_PM_SLEEP
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+static void tegra114_cpu_clock_suspend(void)
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+{
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+ /* switch coresite to clk_m, save off original source */
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+ tegra114_cpu_clk_sctx.clk_csite_src =
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+ readl(clk_base + CLK_SOURCE_CSITE);
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+ writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
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+}
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+
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+static void tegra114_cpu_clock_resume(void)
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+{
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+ writel(tegra114_cpu_clk_sctx.clk_csite_src,
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+ clk_base + CLK_SOURCE_CSITE);
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+}
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+#endif
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+
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static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
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.wait_for_reset = tegra114_wait_cpu_in_reset,
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.disable_clock = tegra114_disable_cpu_clock,
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+#ifdef CONFIG_PM_SLEEP
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+ .suspend = tegra114_cpu_clock_suspend,
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+ .resume = tegra114_cpu_clock_resume,
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+#endif
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};
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static const struct of_device_id pmc_match[] __initconst = {
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