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@@ -79,26 +79,43 @@ static struct platform_device omap_i2c_devices[] = {
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#endif
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};
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-static void __init omap_i2c_mux_pins(int bus_id)
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+#if defined(CONFIG_ARCH_OMAP24XX)
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+static const int omap24xx_pins[][2] = {
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+ { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
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+ { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
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+};
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+#else
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+static const int omap24xx_pins[][2] = {};
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+#endif
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+#if defined(CONFIG_ARCH_OMAP34XX)
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+static const int omap34xx_pins[][2] = {
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+ { K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA},
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+ { AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA},
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+ { AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA},
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+};
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+#else
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+static const int omap34xx_pins[][2] = {};
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+#endif
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+
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+static void __init omap_i2c_mux_pins(int bus)
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{
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- /* TODO: Muxing for OMAP3 */
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- switch (bus_id) {
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- case 1:
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- if (cpu_class_is_omap1()) {
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- omap_cfg_reg(I2C_SCL);
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- omap_cfg_reg(I2C_SDA);
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- } else if (cpu_is_omap24xx()) {
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- omap_cfg_reg(M19_24XX_I2C1_SCL);
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- omap_cfg_reg(L15_24XX_I2C1_SDA);
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- }
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- break;
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- case 2:
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- if (cpu_is_omap24xx()) {
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- omap_cfg_reg(J15_24XX_I2C2_SCL);
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- omap_cfg_reg(H19_24XX_I2C2_SDA);
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- }
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- break;
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+ int scl, sda;
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+
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+ if (cpu_class_is_omap1()) {
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+ scl = I2C_SCL;
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+ sda = I2C_SDA;
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+ } else if (cpu_is_omap24xx()) {
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+ scl = omap24xx_pins[bus][0];
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+ sda = omap24xx_pins[bus][1];
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+ } else if (cpu_is_omap34xx()) {
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+ scl = omap34xx_pins[bus][0];
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+ sda = omap34xx_pins[bus][1];
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+ } else {
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+ return;
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}
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+
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+ omap_cfg_reg(sda);
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+ omap_cfg_reg(scl);
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}
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int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
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@@ -142,6 +159,6 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
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res[1].start = irq;
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}
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- omap_i2c_mux_pins(bus_id);
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+ omap_i2c_mux_pins(bus_id - 1);
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return platform_device_register(pdev);
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}
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