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@@ -768,6 +768,23 @@ static void __init reset_ctrl_regs(void *unused)
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{
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int i;
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+ /*
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+ * v7 debug contains save and restore registers so that debug state
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+ * can be maintained across low-power modes without leaving
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+ * the debug logic powered up. It is IMPLEMENTATION DEFINED whether
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+ * we can write to the debug registers out of reset, so we must
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+ * unlock the OS Lock Access Register to avoid taking undefined
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+ * instruction exceptions later on.
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+ */
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+ if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {
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+ /*
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+ * Unconditionally clear the lock by writing a value
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+ * other than 0xC5ACCE55 to the access register.
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+ */
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+ asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
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+ isb();
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+ }
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+
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if (enable_monitor_mode())
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return;
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@@ -810,17 +827,17 @@ static int __init arch_hw_breakpoint_init(void)
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pr_warning("halting debug mode enabled. Assuming maximum "
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"watchpoint size of 4 bytes.");
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} else {
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- /* Work out the maximum supported watchpoint length. */
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- max_watchpoint_len = get_max_wp_len();
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- pr_info("maximum watchpoint size is %u bytes.\n",
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- max_watchpoint_len);
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-
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/*
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* Reset the breakpoint resources. We assume that a halting
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* debugger will leave the world in a nice state for us.
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*/
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smp_call_function(reset_ctrl_regs, NULL, 1);
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reset_ctrl_regs(NULL);
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+
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+ /* Work out the maximum supported watchpoint length. */
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+ max_watchpoint_len = get_max_wp_len();
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+ pr_info("maximum watchpoint size is %u bytes.\n",
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+ max_watchpoint_len);
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}
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/* Register debug fault handler. */
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