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@@ -68,6 +68,27 @@
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#define DRV_AUTHOR "Bryan Wu <bryan.wu@analog.com>"
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#define DRV_DESC "BF5xx on-chip NAND FLash Controller Driver"
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+/* NFC_STAT Masks */
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+#define NBUSY 0x01 /* Not Busy */
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+#define WB_FULL 0x02 /* Write Buffer Full */
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+#define PG_WR_STAT 0x04 /* Page Write Pending */
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+#define PG_RD_STAT 0x08 /* Page Read Pending */
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+#define WB_EMPTY 0x10 /* Write Buffer Empty */
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+
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+/* NFC_IRQSTAT Masks */
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+#define NBUSYIRQ 0x01 /* Not Busy IRQ */
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+#define WB_OVF 0x02 /* Write Buffer Overflow */
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+#define WB_EDGE 0x04 /* Write Buffer Edge Detect */
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+#define RD_RDY 0x08 /* Read Data Ready */
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+#define WR_DONE 0x10 /* Page Write Done */
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+
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+/* NFC_RST Masks */
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+#define ECC_RST 0x01 /* ECC (and NFC counters) Reset */
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+
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+/* NFC_PGCTL Masks */
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+#define PG_RD_START 0x01 /* Page Read Start */
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+#define PG_WR_START 0x02 /* Page Write Start */
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+
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#ifdef CONFIG_MTD_NAND_BF5XX_HWECC
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static int hardware_ecc = 1;
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#else
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@@ -487,7 +508,7 @@ static void bf5xx_nand_dma_rw(struct mtd_info *mtd,
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* transferred to generate the correct ECC register
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* values.
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*/
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- bfin_write_NFC_RST(0x1);
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+ bfin_write_NFC_RST(ECC_RST);
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SSYNC();
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disable_dma(CH_NFC);
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@@ -497,7 +518,7 @@ static void bf5xx_nand_dma_rw(struct mtd_info *mtd,
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set_dma_config(CH_NFC, 0x0);
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set_dma_start_addr(CH_NFC, (unsigned long) buf);
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-/* The DMAs have different size on BF52x and BF54x */
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+ /* The DMAs have different size on BF52x and BF54x */
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#ifdef CONFIG_BF52x
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set_dma_x_count(CH_NFC, (page_size >> 1));
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set_dma_x_modify(CH_NFC, 2);
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@@ -517,9 +538,9 @@ static void bf5xx_nand_dma_rw(struct mtd_info *mtd,
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/* Start PAGE read/write operation */
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if (is_read)
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- bfin_write_NFC_PGCTL(0x1);
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+ bfin_write_NFC_PGCTL(PG_RD_START);
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else
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- bfin_write_NFC_PGCTL(0x2);
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+ bfin_write_NFC_PGCTL(PG_WR_START);
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wait_for_completion(&info->dma_completion);
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}
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