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@@ -25,7 +25,9 @@
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#include <asm/dma.h>
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#include <asm/mach-types.h>
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+#ifdef CONFIG_SFFSDR_FPGA
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#include <asm/plat-sffsdr/sffsdr-fpga.h>
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+#endif
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#include <mach/mcbsp.h>
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#include <mach/edma.h>
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@@ -43,6 +45,17 @@ static int sffsdr_hw_params(struct snd_pcm_substream *substream,
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int fs;
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int ret = 0;
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+ /* Fsref can be 32000, 44100 or 48000. */
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+ fs = params_rate(params);
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+
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+#ifndef CONFIG_SFFSDR_FPGA
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+ /* Without the FPGA module, the Fs is fixed at 44100 Hz */
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+ if (fs != 44100) {
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+ pr_debug("warning: only 44.1 kHz is supported without SFFSDR FPGA module\n");
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+ return -EINVAL;
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+ }
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+#endif
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+
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/* Set cpu DAI configuration:
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* CLKX and CLKR are the inputs for the Sample Rate Generator.
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* FSX and FSR are outputs, driven by the sample Rate Generator. */
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@@ -53,12 +66,13 @@ static int sffsdr_hw_params(struct snd_pcm_substream *substream,
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if (ret < 0)
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return ret;
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- /* Fsref can be 32000, 44100 or 48000. */
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- fs = params_rate(params);
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-
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pr_debug("sffsdr_hw_params: rate = %d Hz\n", fs);
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+#ifndef CONFIG_SFFSDR_FPGA
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+ return 0;
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+#else
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return sffsdr_fpga_set_codec_fs(fs);
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+#endif
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}
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static struct snd_soc_ops sffsdr_ops = {
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