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@@ -100,6 +100,10 @@ module_param_named(use_prio, use_prio, bool, 0444);
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MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
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"(0/1, default 0)");
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+static int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
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+module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
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+MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)");
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+
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int mlx4_check_port_params(struct mlx4_dev *dev,
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enum mlx4_port_type *port_type)
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{
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@@ -203,12 +207,13 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
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dev->caps.reserved_cqs = dev_cap->reserved_cqs;
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dev->caps.reserved_eqs = dev_cap->reserved_eqs;
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+ dev->caps.mtts_per_seg = 1 << log_mtts_per_seg;
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dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
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- MLX4_MTT_ENTRY_PER_SEG);
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+ dev->caps.mtts_per_seg);
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dev->caps.reserved_mrws = dev_cap->reserved_mrws;
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dev->caps.reserved_uars = dev_cap->reserved_uars;
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dev->caps.reserved_pds = dev_cap->reserved_pds;
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- dev->caps.mtt_entry_sz = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz;
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+ dev->caps.mtt_entry_sz = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
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dev->caps.max_msg_sz = dev_cap->max_msg_sz;
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dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
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dev->caps.flags = dev_cap->flags;
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@@ -1304,6 +1309,11 @@ static int __init mlx4_verify_params(void)
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return -1;
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}
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+ if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) {
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+ printk(KERN_WARNING "mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
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+ return -1;
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+ }
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+
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return 0;
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}
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