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@@ -0,0 +1,694 @@
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+/******************************************************************************
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+ *
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+ * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
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+ *
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+ * Portions of this file are derived from the ipw3945 project, as well
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+ * as portions of the ieee80211 subsystem header files.
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of version 2 of the GNU General Public License as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along with
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+ * this program; if not, write to the Free Software Foundation, Inc.,
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+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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+ *
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+ * The full GNU General Public License is included in this distribution in the
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+ * file called LICENSE.
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+ *
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+ * Contact Information:
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+ * Intel Linux Wireless <ilw@linux.intel.com>
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+ * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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+ *
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+ *****************************************************************************/
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+#include <linux/sched.h>
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+#include <linux/wait.h>
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+
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+#include "iwl-dev.h"
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+#include "iwl-agn.h"
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+#include "iwl-core.h"
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+#include "iwl-io.h"
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+#include "iwl-helpers.h"
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+#include "iwl-trans-int-pcie.h"
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+
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+/******************************************************************************
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+ *
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+ * RX path functions
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+ *
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+ ******************************************************************************/
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+
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+/*
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+ * Rx theory of operation
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+ *
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+ * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
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+ * each of which point to Receive Buffers to be filled by the NIC. These get
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+ * used not only for Rx frames, but for any command response or notification
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+ * from the NIC. The driver and NIC manage the Rx buffers by means
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+ * of indexes into the circular buffer.
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+ *
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+ * Rx Queue Indexes
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+ * The host/firmware share two index registers for managing the Rx buffers.
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+ *
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+ * The READ index maps to the first position that the firmware may be writing
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+ * to -- the driver can read up to (but not including) this position and get
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+ * good data.
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+ * The READ index is managed by the firmware once the card is enabled.
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+ *
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+ * The WRITE index maps to the last position the driver has read from -- the
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+ * position preceding WRITE is the last slot the firmware can place a packet.
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+ *
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+ * The queue is empty (no good data) if WRITE = READ - 1, and is full if
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+ * WRITE = READ.
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+ *
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+ * During initialization, the host sets up the READ queue position to the first
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+ * INDEX position, and WRITE to the last (READ - 1 wrapped)
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+ *
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+ * When the firmware places a packet in a buffer, it will advance the READ index
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+ * and fire the RX interrupt. The driver can then query the READ index and
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+ * process as many packets as possible, moving the WRITE index forward as it
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+ * resets the Rx queue buffers with new memory.
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+ *
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+ * The management in the driver is as follows:
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+ * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
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+ * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
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+ * to replenish the iwl->rxq->rx_free.
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+ * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
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+ * iwl->rxq is replenished and the READ INDEX is updated (updating the
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+ * 'processed' and 'read' driver indexes as well)
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+ * + A received packet is processed and handed to the kernel network stack,
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+ * detached from the iwl->rxq. The driver 'processed' index is updated.
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+ * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
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+ * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
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+ * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
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+ * were enough free buffers and RX_STALLED is set it is cleared.
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+ *
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+ *
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+ * Driver sequence:
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+ *
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+ * iwl_rx_queue_alloc() Allocates rx_free
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+ * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
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+ * iwl_rx_queue_restock
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+ * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
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+ * queue, updates firmware pointers, and updates
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+ * the WRITE index. If insufficient rx_free buffers
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+ * are available, schedules iwl_rx_replenish
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+ *
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+ * -- enable interrupts --
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+ * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
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+ * READ INDEX, detaching the SKB from the pool.
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+ * Moves the packet buffer from queue to rx_used.
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+ * Calls iwl_rx_queue_restock to refill any empty
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+ * slots.
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+ * ...
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+ *
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+ */
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+
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+/**
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+ * iwl_rx_queue_space - Return number of free slots available in queue.
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+ */
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+static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
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+{
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+ int s = q->read - q->write;
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+ if (s <= 0)
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+ s += RX_QUEUE_SIZE;
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+ /* keep some buffer to not confuse full and empty queue */
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+ s -= 2;
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+ if (s < 0)
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+ s = 0;
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+ return s;
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+}
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+
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+/**
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+ * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
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+ */
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+void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,
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+ struct iwl_rx_queue *q)
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+{
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+ unsigned long flags;
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+ u32 reg;
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+
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+ spin_lock_irqsave(&q->lock, flags);
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+
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+ if (q->need_update == 0)
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+ goto exit_unlock;
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+
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+ if (priv->cfg->base_params->shadow_reg_enable) {
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+ /* shadow register enabled */
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+ /* Device expects a multiple of 8 */
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+ q->write_actual = (q->write & ~0x7);
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+ iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write_actual);
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+ } else {
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+ /* If power-saving is in use, make sure device is awake */
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+ if (test_bit(STATUS_POWER_PMI, &priv->status)) {
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+ reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
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+
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+ if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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+ IWL_DEBUG_INFO(priv,
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+ "Rx queue requesting wakeup,"
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+ " GP1 = 0x%x\n", reg);
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+ iwl_set_bit(priv, CSR_GP_CNTRL,
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+ CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ goto exit_unlock;
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+ }
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+
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+ q->write_actual = (q->write & ~0x7);
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+ iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
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+ q->write_actual);
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+
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+ /* Else device is assumed to be awake */
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+ } else {
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+ /* Device expects a multiple of 8 */
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+ q->write_actual = (q->write & ~0x7);
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+ iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
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+ q->write_actual);
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+ }
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+ }
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+ q->need_update = 0;
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+
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+ exit_unlock:
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+ spin_unlock_irqrestore(&q->lock, flags);
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+}
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+
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+/**
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+ * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
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+ */
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+static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
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+ dma_addr_t dma_addr)
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+{
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+ return cpu_to_le32((u32)(dma_addr >> 8));
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+}
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+
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+/**
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+ * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
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+ *
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+ * If there are slots in the RX queue that need to be restocked,
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+ * and we have free pre-allocated buffers, fill the ranks as much
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+ * as we can, pulling from rx_free.
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+ *
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+ * This moves the 'write' index forward to catch up with 'processed', and
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+ * also updates the memory address in the firmware to reference the new
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+ * target buffer.
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+ */
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+static void iwlagn_rx_queue_restock(struct iwl_priv *priv)
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+{
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+ struct iwl_rx_queue *rxq = &priv->rxq;
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+ struct list_head *element;
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+ struct iwl_rx_mem_buffer *rxb;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&rxq->lock, flags);
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+ while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
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+ /* The overwritten rxb must be a used one */
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+ rxb = rxq->queue[rxq->write];
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+ BUG_ON(rxb && rxb->page);
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+
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+ /* Get next free Rx buffer, remove from free list */
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+ element = rxq->rx_free.next;
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+ rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
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+ list_del(element);
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+
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+ /* Point to Rx buffer via next RBD in circular buffer */
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+ rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
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+ rxb->page_dma);
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+ rxq->queue[rxq->write] = rxb;
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+ rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
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+ rxq->free_count--;
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+ }
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+ spin_unlock_irqrestore(&rxq->lock, flags);
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+ /* If the pre-allocated buffer pool is dropping low, schedule to
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+ * refill it */
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+ if (rxq->free_count <= RX_LOW_WATERMARK)
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+ queue_work(priv->workqueue, &priv->rx_replenish);
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+
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+
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+ /* If we've added more space for the firmware to place data, tell it.
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+ * Increment device's write pointer in multiples of 8. */
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+ if (rxq->write_actual != (rxq->write & ~0x7)) {
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+ spin_lock_irqsave(&rxq->lock, flags);
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+ rxq->need_update = 1;
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+ spin_unlock_irqrestore(&rxq->lock, flags);
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+ iwl_rx_queue_update_write_ptr(priv, rxq);
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+ }
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+}
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+
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+/**
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+ * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
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+ *
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+ * When moving to rx_free an SKB is allocated for the slot.
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+ *
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+ * Also restock the Rx queue via iwl_rx_queue_restock.
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+ * This is called as a scheduled work item (except for during initialization)
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+ */
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+static void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
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+{
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+ struct iwl_rx_queue *rxq = &priv->rxq;
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+ struct list_head *element;
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+ struct iwl_rx_mem_buffer *rxb;
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+ struct page *page;
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+ unsigned long flags;
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+ gfp_t gfp_mask = priority;
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+
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+ while (1) {
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+ spin_lock_irqsave(&rxq->lock, flags);
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+ if (list_empty(&rxq->rx_used)) {
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+ spin_unlock_irqrestore(&rxq->lock, flags);
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+ return;
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+ }
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+ spin_unlock_irqrestore(&rxq->lock, flags);
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+
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+ if (rxq->free_count > RX_LOW_WATERMARK)
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+ gfp_mask |= __GFP_NOWARN;
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+
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+ if (priv->hw_params.rx_page_order > 0)
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+ gfp_mask |= __GFP_COMP;
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+
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+ /* Alloc a new receive buffer */
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+ page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
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+ if (!page) {
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+ if (net_ratelimit())
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+ IWL_DEBUG_INFO(priv, "alloc_pages failed, "
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+ "order: %d\n",
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+ priv->hw_params.rx_page_order);
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+
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+ if ((rxq->free_count <= RX_LOW_WATERMARK) &&
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+ net_ratelimit())
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+ IWL_CRIT(priv, "Failed to alloc_pages with %s."
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+ "Only %u free buffers remaining.\n",
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+ priority == GFP_ATOMIC ?
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+ "GFP_ATOMIC" : "GFP_KERNEL",
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+ rxq->free_count);
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+ /* We don't reschedule replenish work here -- we will
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+ * call the restock method and if it still needs
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+ * more buffers it will schedule replenish */
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+ return;
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+ }
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+
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+ spin_lock_irqsave(&rxq->lock, flags);
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+
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+ if (list_empty(&rxq->rx_used)) {
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+ spin_unlock_irqrestore(&rxq->lock, flags);
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+ __free_pages(page, priv->hw_params.rx_page_order);
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+ return;
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+ }
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+ element = rxq->rx_used.next;
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+ rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
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+ list_del(element);
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+
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+ spin_unlock_irqrestore(&rxq->lock, flags);
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+
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+ BUG_ON(rxb->page);
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+ rxb->page = page;
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+ /* Get physical address of the RB */
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+ rxb->page_dma = dma_map_page(priv->bus.dev, page, 0,
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+ PAGE_SIZE << priv->hw_params.rx_page_order,
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+ DMA_FROM_DEVICE);
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+ /* dma address must be no more than 36 bits */
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+ BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
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+ /* and also 256 byte aligned! */
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+ BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
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+
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+ spin_lock_irqsave(&rxq->lock, flags);
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+
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+ list_add_tail(&rxb->list, &rxq->rx_free);
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+ rxq->free_count++;
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+
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+ spin_unlock_irqrestore(&rxq->lock, flags);
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+ }
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+}
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+
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+void iwlagn_rx_replenish(struct iwl_priv *priv)
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+{
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+ unsigned long flags;
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+
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+ iwlagn_rx_allocate(priv, GFP_KERNEL);
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+
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+ spin_lock_irqsave(&priv->lock, flags);
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+ iwlagn_rx_queue_restock(priv);
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+ spin_unlock_irqrestore(&priv->lock, flags);
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+}
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+
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+static void iwlagn_rx_replenish_now(struct iwl_priv *priv)
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+{
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+ iwlagn_rx_allocate(priv, GFP_ATOMIC);
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+
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+ iwlagn_rx_queue_restock(priv);
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+}
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+
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+void iwl_bg_rx_replenish(struct work_struct *data)
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+{
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+ struct iwl_priv *priv =
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+ container_of(data, struct iwl_priv, rx_replenish);
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+
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+ if (test_bit(STATUS_EXIT_PENDING, &priv->status))
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+ return;
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+
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+ mutex_lock(&priv->mutex);
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+ iwlagn_rx_replenish(priv);
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+ mutex_unlock(&priv->mutex);
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+}
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+
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+/**
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+ * iwl_rx_handle - Main entry function for receiving responses from uCode
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+ *
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+ * Uses the priv->rx_handlers callback function array to invoke
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+ * the appropriate handlers, including command responses,
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+ * frame-received notifications, and other notifications.
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+ */
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+static void iwl_rx_handle(struct iwl_priv *priv)
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+{
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+ struct iwl_rx_mem_buffer *rxb;
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+ struct iwl_rx_packet *pkt;
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+ struct iwl_rx_queue *rxq = &priv->rxq;
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+ u32 r, i;
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+ int reclaim;
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+ unsigned long flags;
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+ u8 fill_rx = 0;
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+ u32 count = 8;
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+ int total_empty;
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+
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+ /* uCode's read index (stored in shared DRAM) indicates the last Rx
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+ * buffer that the driver may process (last buffer filled by ucode). */
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+ r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
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+ i = rxq->read;
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+
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+ /* Rx interrupt, but nothing sent from uCode */
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+ if (i == r)
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+ IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
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|
|
+
|
|
|
+ /* calculate total frames need to be restock after handling RX */
|
|
|
+ total_empty = r - rxq->write_actual;
|
|
|
+ if (total_empty < 0)
|
|
|
+ total_empty += RX_QUEUE_SIZE;
|
|
|
+
|
|
|
+ if (total_empty > (RX_QUEUE_SIZE / 2))
|
|
|
+ fill_rx = 1;
|
|
|
+
|
|
|
+ while (i != r) {
|
|
|
+ int len;
|
|
|
+
|
|
|
+ rxb = rxq->queue[i];
|
|
|
+
|
|
|
+ /* If an RXB doesn't have a Rx queue slot associated with it,
|
|
|
+ * then a bug has been introduced in the queue refilling
|
|
|
+ * routines -- catch it here */
|
|
|
+ if (WARN_ON(rxb == NULL)) {
|
|
|
+ i = (i + 1) & RX_QUEUE_MASK;
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ rxq->queue[i] = NULL;
|
|
|
+
|
|
|
+ dma_unmap_page(priv->bus.dev, rxb->page_dma,
|
|
|
+ PAGE_SIZE << priv->hw_params.rx_page_order,
|
|
|
+ DMA_FROM_DEVICE);
|
|
|
+ pkt = rxb_addr(rxb);
|
|
|
+
|
|
|
+ IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
|
|
|
+ i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
|
|
|
+
|
|
|
+ len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
|
|
|
+ len += sizeof(u32); /* account for status word */
|
|
|
+ trace_iwlwifi_dev_rx(priv, pkt, len);
|
|
|
+
|
|
|
+ /* Reclaim a command buffer only if this packet is a response
|
|
|
+ * to a (driver-originated) command.
|
|
|
+ * If the packet (e.g. Rx frame) originated from uCode,
|
|
|
+ * there is no command buffer to reclaim.
|
|
|
+ * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
|
|
|
+ * but apparently a few don't get set; catch them here. */
|
|
|
+ reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
|
|
|
+ (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
|
|
|
+ (pkt->hdr.cmd != REPLY_RX) &&
|
|
|
+ (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
|
|
|
+ (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
|
|
|
+ (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
|
|
|
+ (pkt->hdr.cmd != REPLY_TX);
|
|
|
+
|
|
|
+ iwl_rx_dispatch(priv, rxb);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * XXX: After here, we should always check rxb->page
|
|
|
+ * against NULL before touching it or its virtual
|
|
|
+ * memory (pkt). Because some rx_handler might have
|
|
|
+ * already taken or freed the pages.
|
|
|
+ */
|
|
|
+
|
|
|
+ if (reclaim) {
|
|
|
+ /* Invoke any callbacks, transfer the buffer to caller,
|
|
|
+ * and fire off the (possibly) blocking
|
|
|
+ * trans_send_cmd()
|
|
|
+ * as we reclaim the driver command queue */
|
|
|
+ if (rxb->page)
|
|
|
+ iwl_tx_cmd_complete(priv, rxb);
|
|
|
+ else
|
|
|
+ IWL_WARN(priv, "Claim null rxb?\n");
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Reuse the page if possible. For notification packets and
|
|
|
+ * SKBs that fail to Rx correctly, add them back into the
|
|
|
+ * rx_free list for reuse later. */
|
|
|
+ spin_lock_irqsave(&rxq->lock, flags);
|
|
|
+ if (rxb->page != NULL) {
|
|
|
+ rxb->page_dma = dma_map_page(priv->bus.dev, rxb->page,
|
|
|
+ 0, PAGE_SIZE << priv->hw_params.rx_page_order,
|
|
|
+ DMA_FROM_DEVICE);
|
|
|
+ list_add_tail(&rxb->list, &rxq->rx_free);
|
|
|
+ rxq->free_count++;
|
|
|
+ } else
|
|
|
+ list_add_tail(&rxb->list, &rxq->rx_used);
|
|
|
+
|
|
|
+ spin_unlock_irqrestore(&rxq->lock, flags);
|
|
|
+
|
|
|
+ i = (i + 1) & RX_QUEUE_MASK;
|
|
|
+ /* If there are a lot of unused frames,
|
|
|
+ * restock the Rx queue so ucode wont assert. */
|
|
|
+ if (fill_rx) {
|
|
|
+ count++;
|
|
|
+ if (count >= 8) {
|
|
|
+ rxq->read = i;
|
|
|
+ iwlagn_rx_replenish_now(priv);
|
|
|
+ count = 0;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Backtrack one entry */
|
|
|
+ rxq->read = i;
|
|
|
+ if (fill_rx)
|
|
|
+ iwlagn_rx_replenish_now(priv);
|
|
|
+ else
|
|
|
+ iwlagn_rx_queue_restock(priv);
|
|
|
+}
|
|
|
+
|
|
|
+/* tasklet for iwlagn interrupt */
|
|
|
+void iwl_irq_tasklet(struct iwl_priv *priv)
|
|
|
+{
|
|
|
+ u32 inta = 0;
|
|
|
+ u32 handled = 0;
|
|
|
+ unsigned long flags;
|
|
|
+ u32 i;
|
|
|
+#ifdef CONFIG_IWLWIFI_DEBUG
|
|
|
+ u32 inta_mask;
|
|
|
+#endif
|
|
|
+
|
|
|
+ spin_lock_irqsave(&priv->lock, flags);
|
|
|
+
|
|
|
+ /* Ack/clear/reset pending uCode interrupts.
|
|
|
+ * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
|
|
|
+ */
|
|
|
+ /* There is a hardware bug in the interrupt mask function that some
|
|
|
+ * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
|
|
|
+ * they are disabled in the CSR_INT_MASK register. Furthermore the
|
|
|
+ * ICT interrupt handling mechanism has another bug that might cause
|
|
|
+ * these unmasked interrupts fail to be detected. We workaround the
|
|
|
+ * hardware bugs here by ACKing all the possible interrupts so that
|
|
|
+ * interrupt coalescing can still be achieved.
|
|
|
+ */
|
|
|
+ iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
|
|
|
+
|
|
|
+ inta = priv->_agn.inta;
|
|
|
+
|
|
|
+#ifdef CONFIG_IWLWIFI_DEBUG
|
|
|
+ if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
|
|
|
+ /* just for debug */
|
|
|
+ inta_mask = iwl_read32(priv, CSR_INT_MASK);
|
|
|
+ IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
|
|
|
+ inta, inta_mask);
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
+ spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
+
|
|
|
+ /* saved interrupt in inta variable now we can reset priv->_agn.inta */
|
|
|
+ priv->_agn.inta = 0;
|
|
|
+
|
|
|
+ /* Now service all interrupt bits discovered above. */
|
|
|
+ if (inta & CSR_INT_BIT_HW_ERR) {
|
|
|
+ IWL_ERR(priv, "Hardware error detected. Restarting.\n");
|
|
|
+
|
|
|
+ /* Tell the device to stop sending interrupts */
|
|
|
+ iwl_disable_interrupts(priv);
|
|
|
+
|
|
|
+ priv->isr_stats.hw++;
|
|
|
+ iwl_irq_handle_error(priv);
|
|
|
+
|
|
|
+ handled |= CSR_INT_BIT_HW_ERR;
|
|
|
+
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+#ifdef CONFIG_IWLWIFI_DEBUG
|
|
|
+ if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
|
|
|
+ /* NIC fires this, but we don't use it, redundant with WAKEUP */
|
|
|
+ if (inta & CSR_INT_BIT_SCD) {
|
|
|
+ IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
|
|
|
+ "the frame/frames.\n");
|
|
|
+ priv->isr_stats.sch++;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Alive notification via Rx interrupt will do the real work */
|
|
|
+ if (inta & CSR_INT_BIT_ALIVE) {
|
|
|
+ IWL_DEBUG_ISR(priv, "Alive interrupt\n");
|
|
|
+ priv->isr_stats.alive++;
|
|
|
+ }
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ /* Safely ignore these bits for debug checks below */
|
|
|
+ inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
|
|
|
+
|
|
|
+ /* HW RF KILL switch toggled */
|
|
|
+ if (inta & CSR_INT_BIT_RF_KILL) {
|
|
|
+ int hw_rf_kill = 0;
|
|
|
+ if (!(iwl_read32(priv, CSR_GP_CNTRL) &
|
|
|
+ CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
|
|
|
+ hw_rf_kill = 1;
|
|
|
+
|
|
|
+ IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
|
|
|
+ hw_rf_kill ? "disable radio" : "enable radio");
|
|
|
+
|
|
|
+ priv->isr_stats.rfkill++;
|
|
|
+
|
|
|
+ /* driver only loads ucode once setting the interface up.
|
|
|
+ * the driver allows loading the ucode even if the radio
|
|
|
+ * is killed. Hence update the killswitch state here. The
|
|
|
+ * rfkill handler will care about restarting if needed.
|
|
|
+ */
|
|
|
+ if (!test_bit(STATUS_ALIVE, &priv->status)) {
|
|
|
+ if (hw_rf_kill)
|
|
|
+ set_bit(STATUS_RF_KILL_HW, &priv->status);
|
|
|
+ else
|
|
|
+ clear_bit(STATUS_RF_KILL_HW, &priv->status);
|
|
|
+ wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
|
|
|
+ }
|
|
|
+
|
|
|
+ handled |= CSR_INT_BIT_RF_KILL;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Chip got too hot and stopped itself */
|
|
|
+ if (inta & CSR_INT_BIT_CT_KILL) {
|
|
|
+ IWL_ERR(priv, "Microcode CT kill error detected.\n");
|
|
|
+ priv->isr_stats.ctkill++;
|
|
|
+ handled |= CSR_INT_BIT_CT_KILL;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Error detected by uCode */
|
|
|
+ if (inta & CSR_INT_BIT_SW_ERR) {
|
|
|
+ IWL_ERR(priv, "Microcode SW error detected. "
|
|
|
+ " Restarting 0x%X.\n", inta);
|
|
|
+ priv->isr_stats.sw++;
|
|
|
+ iwl_irq_handle_error(priv);
|
|
|
+ handled |= CSR_INT_BIT_SW_ERR;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* uCode wakes up after power-down sleep */
|
|
|
+ if (inta & CSR_INT_BIT_WAKEUP) {
|
|
|
+ IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
|
|
|
+ iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
|
|
|
+ for (i = 0; i < priv->hw_params.max_txq_num; i++)
|
|
|
+ iwl_txq_update_write_ptr(priv, &priv->txq[i]);
|
|
|
+
|
|
|
+ priv->isr_stats.wakeup++;
|
|
|
+
|
|
|
+ handled |= CSR_INT_BIT_WAKEUP;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* All uCode command responses, including Tx command responses,
|
|
|
+ * Rx "responses" (frame-received notification), and other
|
|
|
+ * notifications from uCode come through here*/
|
|
|
+ if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
|
|
|
+ CSR_INT_BIT_RX_PERIODIC)) {
|
|
|
+ IWL_DEBUG_ISR(priv, "Rx interrupt\n");
|
|
|
+ if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
|
|
|
+ handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
|
|
|
+ iwl_write32(priv, CSR_FH_INT_STATUS,
|
|
|
+ CSR_FH_INT_RX_MASK);
|
|
|
+ }
|
|
|
+ if (inta & CSR_INT_BIT_RX_PERIODIC) {
|
|
|
+ handled |= CSR_INT_BIT_RX_PERIODIC;
|
|
|
+ iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
|
|
|
+ }
|
|
|
+ /* Sending RX interrupt require many steps to be done in the
|
|
|
+ * the device:
|
|
|
+ * 1- write interrupt to current index in ICT table.
|
|
|
+ * 2- dma RX frame.
|
|
|
+ * 3- update RX shared data to indicate last write index.
|
|
|
+ * 4- send interrupt.
|
|
|
+ * This could lead to RX race, driver could receive RX interrupt
|
|
|
+ * but the shared data changes does not reflect this;
|
|
|
+ * periodic interrupt will detect any dangling Rx activity.
|
|
|
+ */
|
|
|
+
|
|
|
+ /* Disable periodic interrupt; we use it as just a one-shot. */
|
|
|
+ iwl_write8(priv, CSR_INT_PERIODIC_REG,
|
|
|
+ CSR_INT_PERIODIC_DIS);
|
|
|
+ iwl_rx_handle(priv);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Enable periodic interrupt in 8 msec only if we received
|
|
|
+ * real RX interrupt (instead of just periodic int), to catch
|
|
|
+ * any dangling Rx interrupt. If it was just the periodic
|
|
|
+ * interrupt, there was no dangling Rx activity, and no need
|
|
|
+ * to extend the periodic interrupt; one-shot is enough.
|
|
|
+ */
|
|
|
+ if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
|
|
|
+ iwl_write8(priv, CSR_INT_PERIODIC_REG,
|
|
|
+ CSR_INT_PERIODIC_ENA);
|
|
|
+
|
|
|
+ priv->isr_stats.rx++;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* This "Tx" DMA channel is used only for loading uCode */
|
|
|
+ if (inta & CSR_INT_BIT_FH_TX) {
|
|
|
+ iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
|
|
|
+ IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
|
|
|
+ priv->isr_stats.tx++;
|
|
|
+ handled |= CSR_INT_BIT_FH_TX;
|
|
|
+ /* Wake up uCode load routine, now that load is complete */
|
|
|
+ priv->ucode_write_complete = 1;
|
|
|
+ wake_up_interruptible(&priv->wait_command_queue);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (inta & ~handled) {
|
|
|
+ IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
|
|
|
+ priv->isr_stats.unhandled++;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (inta & ~(priv->inta_mask)) {
|
|
|
+ IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
|
|
|
+ inta & ~priv->inta_mask);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Re-enable all interrupts */
|
|
|
+ /* only Re-enable if disabled by irq */
|
|
|
+ if (test_bit(STATUS_INT_ENABLED, &priv->status))
|
|
|
+ iwl_enable_interrupts(priv);
|
|
|
+ /* Re-enable RF_KILL if it occurred */
|
|
|
+ else if (handled & CSR_INT_BIT_RF_KILL)
|
|
|
+ iwl_enable_rfkill_int(priv);
|
|
|
+}
|
|
|
+
|
Emmanuel Grumbach