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@@ -966,10 +966,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
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if (ret)
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goto kfree_devname;
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- dev_priv->mm.gtt_mapping =
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- io_mapping_create_wc(dev->agp->base,
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- dev->agp->agp_info.aper_size * 1024*1024);
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-
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/* Allow hardware batchbuffers unless told otherwise.
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*/
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dev_priv->allow_batchbuffer = 1;
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@@ -1081,6 +1077,23 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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goto free_priv;
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}
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+ dev_priv->mm.gtt_mapping =
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+ io_mapping_create_wc(dev->agp->base,
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+ dev->agp->agp_info.aper_size * 1024*1024);
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+ /* Set up a WC MTRR for non-PAT systems. This is more common than
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+ * one would think, because the kernel disables PAT on first
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+ * generation Core chips because WC PAT gets overridden by a UC
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+ * MTRR if present. Even if a UC MTRR isn't present.
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+ */
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+ dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
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+ dev->agp->agp_info.aper_size *
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+ 1024 * 1024,
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+ MTRR_TYPE_WRCOMB, 1);
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+ if (dev_priv->mm.gtt_mtrr < 0) {
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+ DRM_INFO("MTRR allocation failed\n. Graphics "
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+ "performance may suffer.\n");
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+ }
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+
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#ifdef CONFIG_HIGHMEM64G
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/* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */
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dev_priv->has_gem = 0;
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@@ -1145,8 +1158,14 @@ int i915_driver_unload(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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+ io_mapping_free(dev_priv->mm.gtt_mapping);
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+ if (dev_priv->mm.gtt_mtrr >= 0) {
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+ mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
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+ dev->agp->agp_info.aper_size * 1024 * 1024);
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+ dev_priv->mm.gtt_mtrr = -1;
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+ }
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+
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if (drm_core_check_feature(dev, DRIVER_MODESET)) {
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- io_mapping_free(dev_priv->mm.gtt_mapping);
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drm_irq_uninstall(dev);
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}
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