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@@ -313,10 +313,16 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
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return -ENODEV;
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}
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-static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
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+static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
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{
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- struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
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- u32 mask = (u32) irq_data_get_irq_handler_data(d);
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+ struct davinci_gpio_controller *d;
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+ struct davinci_gpio_regs __iomem *g;
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+ struct davinci_soc_info *soc_info = &davinci_soc_info;
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+ u32 mask;
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+
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+ d = (struct davinci_gpio_controller *)data->handler_data;
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+ g = (struct davinci_gpio_regs __iomem *)d->regs;
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+ mask = __gpio_mask(data->irq - soc_info->gpio_irq);
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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return -EINVAL;
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@@ -400,8 +406,7 @@ static int __init davinci_gpio_irq_setup(void)
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/* set the direct IRQs up to use that irqchip */
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for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
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irq_set_chip(irq, &gpio_irqchip_unbanked);
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- irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
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- irq_set_chip_data(irq, (__force void *)g);
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+ irq_set_handler_data(irq, &chips[gpio / 32]);
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irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
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}
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