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@@ -374,13 +374,11 @@ static int dmacontroller_setup(struct bcm43xx_dmaring *ring)
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if (ring->tx) {
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if (ring->tx) {
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/* Set Transmit Control register to "transmit enable" */
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/* Set Transmit Control register to "transmit enable" */
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- bcm43xx_write32(ring->bcm,
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- ring->mmio_base + BCM43xx_DMA_TX_CONTROL,
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- BCM43xx_DMA_TXCTRL_ENABLE);
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+ bcm43xx_dma_write(ring, BCM43xx_DMA_TX_CONTROL,
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+ BCM43xx_DMA_TXCTRL_ENABLE);
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/* Set Transmit Descriptor ring address. */
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/* Set Transmit Descriptor ring address. */
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- bcm43xx_write32(ring->bcm,
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- ring->mmio_base + BCM43xx_DMA_TX_DESC_RING,
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- ring->dmabase + ring->memoffset);
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+ bcm43xx_dma_write(ring, BCM43xx_DMA_TX_DESC_RING,
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+ ring->dmabase + ring->memoffset);
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} else {
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} else {
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err = alloc_initial_descbuffers(ring);
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err = alloc_initial_descbuffers(ring);
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if (err)
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if (err)
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@@ -388,17 +386,12 @@ static int dmacontroller_setup(struct bcm43xx_dmaring *ring)
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/* Set Receive Control "receive enable" and frame offset */
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/* Set Receive Control "receive enable" and frame offset */
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value = (ring->frameoffset << BCM43xx_DMA_RXCTRL_FRAMEOFF_SHIFT);
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value = (ring->frameoffset << BCM43xx_DMA_RXCTRL_FRAMEOFF_SHIFT);
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value |= BCM43xx_DMA_RXCTRL_ENABLE;
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value |= BCM43xx_DMA_RXCTRL_ENABLE;
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- bcm43xx_write32(ring->bcm,
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- ring->mmio_base + BCM43xx_DMA_RX_CONTROL,
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- value);
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+ bcm43xx_dma_write(ring, BCM43xx_DMA_RX_CONTROL, value);
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/* Set Receive Descriptor ring address. */
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/* Set Receive Descriptor ring address. */
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- bcm43xx_write32(ring->bcm,
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- ring->mmio_base + BCM43xx_DMA_RX_DESC_RING,
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- ring->dmabase + ring->memoffset);
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+ bcm43xx_dma_write(ring, BCM43xx_DMA_RX_DESC_RING,
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+ ring->dmabase + ring->memoffset);
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/* Init the descriptor pointer. */
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/* Init the descriptor pointer. */
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- bcm43xx_write32(ring->bcm,
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- ring->mmio_base + BCM43xx_DMA_RX_DESC_INDEX,
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- 200);
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+ bcm43xx_dma_write(ring, BCM43xx_DMA_RX_DESC_INDEX, 200);
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}
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}
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out:
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out:
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@@ -411,15 +404,11 @@ static void dmacontroller_cleanup(struct bcm43xx_dmaring *ring)
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if (ring->tx) {
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if (ring->tx) {
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bcm43xx_dmacontroller_tx_reset(ring->bcm, ring->mmio_base);
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bcm43xx_dmacontroller_tx_reset(ring->bcm, ring->mmio_base);
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/* Zero out Transmit Descriptor ring address. */
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/* Zero out Transmit Descriptor ring address. */
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- bcm43xx_write32(ring->bcm,
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- ring->mmio_base + BCM43xx_DMA_TX_DESC_RING,
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- 0x00000000);
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+ bcm43xx_dma_write(ring, BCM43xx_DMA_TX_DESC_RING, 0);
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} else {
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} else {
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bcm43xx_dmacontroller_rx_reset(ring->bcm, ring->mmio_base);
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bcm43xx_dmacontroller_rx_reset(ring->bcm, ring->mmio_base);
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/* Zero out Receive Descriptor ring address. */
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/* Zero out Receive Descriptor ring address. */
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- bcm43xx_write32(ring->bcm,
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- ring->mmio_base + BCM43xx_DMA_RX_DESC_RING,
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- 0x00000000);
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+ bcm43xx_dma_write(ring, BCM43xx_DMA_RX_DESC_RING, 0);
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}
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}
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}
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}
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@@ -698,9 +687,8 @@ static void dmacontroller_poke_tx(struct bcm43xx_dmaring *ring,
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*/
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*/
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wmb();
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wmb();
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slot = next_slot(ring, slot);
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slot = next_slot(ring, slot);
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- bcm43xx_write32(ring->bcm,
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- ring->mmio_base + BCM43xx_DMA_TX_DESC_INDEX,
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- (u32)(slot * sizeof(struct bcm43xx_dmadesc)));
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+ bcm43xx_dma_write(ring, BCM43xx_DMA_TX_DESC_INDEX,
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+ (u32)(slot * sizeof(struct bcm43xx_dmadesc)));
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}
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}
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static int dma_tx_fragment(struct bcm43xx_dmaring *ring,
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static int dma_tx_fragment(struct bcm43xx_dmaring *ring,
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@@ -940,7 +928,7 @@ void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
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#endif
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#endif
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assert(!ring->tx);
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assert(!ring->tx);
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- status = bcm43xx_read32(ring->bcm, ring->mmio_base + BCM43xx_DMA_RX_STATUS);
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+ status = bcm43xx_dma_read(ring, BCM43xx_DMA_RX_STATUS);
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descptr = (status & BCM43xx_DMA_RXSTAT_DPTR_MASK);
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descptr = (status & BCM43xx_DMA_RXSTAT_DPTR_MASK);
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current_slot = descptr / sizeof(struct bcm43xx_dmadesc);
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current_slot = descptr / sizeof(struct bcm43xx_dmadesc);
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assert(current_slot >= 0 && current_slot < ring->nr_slots);
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assert(current_slot >= 0 && current_slot < ring->nr_slots);
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@@ -953,10 +941,27 @@ void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
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ring->max_used_slots = used_slots;
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ring->max_used_slots = used_slots;
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#endif
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#endif
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}
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}
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- bcm43xx_write32(ring->bcm,
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- ring->mmio_base + BCM43xx_DMA_RX_DESC_INDEX,
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- (u32)(slot * sizeof(struct bcm43xx_dmadesc)));
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+ bcm43xx_dma_write(ring, BCM43xx_DMA_RX_DESC_INDEX,
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+ (u32)(slot * sizeof(struct bcm43xx_dmadesc)));
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ring->current_slot = slot;
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ring->current_slot = slot;
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}
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}
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+void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring)
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+{
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+ assert(ring->tx);
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+ bcm43xx_power_saving_ctl_bits(ring->bcm, -1, 1);
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+ bcm43xx_dma_write(ring, BCM43xx_DMA_TX_CONTROL,
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+ bcm43xx_dma_read(ring, BCM43xx_DMA_TX_CONTROL)
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+ | BCM43xx_DMA_TXCTRL_SUSPEND);
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+}
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+
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+void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring)
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+{
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+ assert(ring->tx);
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+ bcm43xx_dma_write(ring, BCM43xx_DMA_TX_CONTROL,
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+ bcm43xx_dma_read(ring, BCM43xx_DMA_TX_CONTROL)
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+ & ~BCM43xx_DMA_TXCTRL_SUSPEND);
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+ bcm43xx_power_saving_ctl_bits(ring->bcm, -1, -1);
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+}
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+
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/* vim: set ts=8 sw=8 sts=8: */
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/* vim: set ts=8 sw=8 sts=8: */
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