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@@ -111,6 +111,7 @@ struct clk {
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#define CLK_PLL BIT(4) /* PLL-derived clock */
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#define CLK_PLL BIT(4) /* PLL-derived clock */
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#define PRE_PLL BIT(5) /* source is before PLL mult/div */
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#define PRE_PLL BIT(5) /* source is before PLL mult/div */
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#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
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#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
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+#define PSC_FORCE BIT(7) /* Force module state transtition */
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#define CLK(dev, con, ck) \
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#define CLK(dev, con, ck) \
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{ \
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{ \
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