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@@ -1105,13 +1105,26 @@ static u32 pl08x_cctl(u32 cctl)
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return cctl | PL080_CONTROL_PROT_SYS;
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}
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+static u32 pl08x_width(enum dma_slave_buswidth width)
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+{
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+ switch (width) {
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+ case DMA_SLAVE_BUSWIDTH_1_BYTE:
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+ return PL080_WIDTH_8BIT;
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+ case DMA_SLAVE_BUSWIDTH_2_BYTES:
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+ return PL080_WIDTH_16BIT;
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+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
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+ return PL080_WIDTH_32BIT;
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+ }
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+ return ~0;
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+}
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+
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static int dma_set_runtime_config(struct dma_chan *chan,
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struct dma_slave_config *config)
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{
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struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
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struct pl08x_driver_data *pl08x = plchan->host;
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enum dma_slave_buswidth addr_width;
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- u32 maxburst;
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+ u32 width, maxburst;
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u32 cctl = 0;
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int i;
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@@ -1132,25 +1145,16 @@ static int dma_set_runtime_config(struct dma_chan *chan,
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return -EINVAL;
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}
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- switch (addr_width) {
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- case DMA_SLAVE_BUSWIDTH_1_BYTE:
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- cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
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- (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
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- break;
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- case DMA_SLAVE_BUSWIDTH_2_BYTES:
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- cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
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- (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
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- break;
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- case DMA_SLAVE_BUSWIDTH_4_BYTES:
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- cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
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- (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
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- break;
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- default:
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+ width = pl08x_width(addr_width);
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+ if (width == ~0) {
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dev_err(&pl08x->adev->dev,
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"bad runtime_config: alien address width\n");
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return -EINVAL;
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}
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+ cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
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+ cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
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+
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/*
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* Now decide on a maxburst:
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* If this channel will only request single transfers, set this
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