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@@ -75,21 +75,16 @@
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#include "iwl-agn-hw.h"
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#include "internal.h"
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-static void iwl_pcie_set_pwr_vmain(struct iwl_trans *trans)
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+static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
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{
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-/*
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- * (for documentation purposes)
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- * to set power to V_AUX, do:
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-
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- if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
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- iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
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- APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
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- ~APMG_PS_CTRL_MSK_PWR_SRC);
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- */
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-
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- iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
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- APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
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- ~APMG_PS_CTRL_MSK_PWR_SRC);
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+ if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
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+ iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
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+ APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
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+ ~APMG_PS_CTRL_MSK_PWR_SRC);
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+ else
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+ iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
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+ APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
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+ ~APMG_PS_CTRL_MSK_PWR_SRC);
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}
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/* PCI registers */
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@@ -259,7 +254,7 @@ static int iwl_pcie_nic_init(struct iwl_trans *trans)
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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- iwl_pcie_set_pwr_vmain(trans);
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+ iwl_pcie_set_pwr(trans, false);
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iwl_op_mode_nic_config(trans->op_mode);
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@@ -545,15 +540,76 @@ static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
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clear_bit(STATUS_RFKILL, &trans_pcie->status);
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}
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-static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
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+static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans)
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{
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/* let the ucode operate on its own */
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iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
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CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
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iwl_disable_interrupts(trans);
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+ iwl_pcie_disable_ict(trans);
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+
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ iwl_clear_bit(trans, CSR_GP_CNTRL,
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+ CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+
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+ /*
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+ * reset TX queues -- some of their registers reset during S3
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+ * so if we don't reset everything here the D3 image would try
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+ * to execute some invalid memory upon resume
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+ */
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+ iwl_trans_pcie_tx_reset(trans);
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+
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+ iwl_pcie_set_pwr(trans, true);
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+}
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+
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+static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
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+ enum iwl_d3_status *status)
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+{
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+ u32 val;
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+ int ret;
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+
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+ iwl_pcie_set_pwr(trans, false);
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+
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+ val = iwl_read32(trans, CSR_RESET);
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+ if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
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+ *status = IWL_D3_STATUS_RESET;
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+ return 0;
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+ }
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+
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+ /*
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+ * Also enables interrupts - none will happen as the device doesn't
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+ * know we're waking it up, only when the opmode actually tells it
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+ * after this call.
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+ */
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+ iwl_pcie_reset_ict(trans);
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+
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+ iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+
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+ ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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+ CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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+ CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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+ 25000);
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+ if (ret) {
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+ IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
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+ return ret;
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+ }
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+
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+ iwl_trans_pcie_tx_reset(trans);
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+
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+ ret = iwl_pcie_rx_init(trans);
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+ if (ret) {
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+ IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
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+ return ret;
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+ }
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+
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+ iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
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+ CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
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+
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+ *status = IWL_D3_STATUS_ALIVE;
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+ return 0;
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}
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static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
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@@ -719,9 +775,6 @@ static int iwl_trans_pcie_resume(struct iwl_trans *trans)
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hw_rfkill = iwl_is_rfkill_set(trans);
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iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
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- if (!hw_rfkill)
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- iwl_enable_interrupts(trans);
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-
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return 0;
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}
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#endif /* CONFIG_PM_SLEEP */
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@@ -818,7 +871,8 @@ static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
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if (iwl_trans_grab_nic_access(trans, false)) {
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iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
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for (offs = 0; offs < dwords; offs++)
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- iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);
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+ iwl_write32(trans, HBUS_TARG_MEM_WDAT,
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+ vals ? vals[offs] : 0);
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iwl_trans_release_nic_access(trans);
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} else {
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ret = -EBUSY;
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@@ -836,6 +890,8 @@ static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
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struct iwl_queue *q;
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int cnt;
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unsigned long now = jiffies;
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+ u32 scd_sram_addr;
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+ u8 buf[16];
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int ret = 0;
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/* waiting for all the tx frames complete might take a while */
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@@ -849,11 +905,50 @@ static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
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msleep(1);
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if (q->read_ptr != q->write_ptr) {
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- IWL_ERR(trans, "fail to flush all tx fifo queues\n");
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+ IWL_ERR(trans,
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+ "fail to flush all tx fifo queues Q %d\n", cnt);
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ret = -ETIMEDOUT;
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break;
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}
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}
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+
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+ if (!ret)
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+ return 0;
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+
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+ IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
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+ txq->q.read_ptr, txq->q.write_ptr);
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+
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+ scd_sram_addr = trans_pcie->scd_base_addr +
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+ SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
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+ iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
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+
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+ iwl_print_hex_error(trans, buf, sizeof(buf));
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+
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+ for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
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+ IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
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+ iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
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+
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+ for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
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+ u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
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+ u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
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+ bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
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+ u32 tbl_dw =
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+ iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
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+ SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
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+
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+ if (cnt & 0x1)
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+ tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
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+ else
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+ tbl_dw = tbl_dw & 0x0000FFFF;
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+
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+ IWL_ERR(trans,
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+ "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
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+ cnt, active ? "" : "in", fifo, tbl_dw,
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+ iwl_read_prph(trans,
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+ SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
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+ iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
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+ }
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+
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return ret;
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}
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@@ -1281,7 +1376,8 @@ static const struct iwl_trans_ops trans_ops_pcie = {
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.start_fw = iwl_trans_pcie_start_fw,
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.stop_device = iwl_trans_pcie_stop_device,
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- .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
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+ .d3_suspend = iwl_trans_pcie_d3_suspend,
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+ .d3_resume = iwl_trans_pcie_d3_resume,
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.send_cmd = iwl_trans_pcie_send_hcmd,
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John W. Linville