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@@ -425,8 +425,6 @@ nv50_graph_register(struct drm_device *dev)
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NVOBJ_CLASS(dev, 0x0030, GR); /* null */
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NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
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NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
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- NVOBJ_CLASS(dev, 0x50c0, GR); /* compute */
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- NVOBJ_CLASS(dev, 0x85c0, GR); /* compute (nva3, nva5, nva8) */
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/* tesla */
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if (dev_priv->chipset == 0x50)
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@@ -452,6 +450,14 @@ nv50_graph_register(struct drm_device *dev)
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}
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}
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+ /* compute */
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+ if (dev_priv->chipset <= 0xa0 ||
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+ dev_priv->chipset == 0xaa ||
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+ dev_priv->chipset == 0xac)
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+ NVOBJ_CLASS(dev, 0x50c0, GR);
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+ else
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+ NVOBJ_CLASS(dev, 0x85c0, GR);
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+
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dev_priv->engine.graph.registered = true;
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return 0;
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}
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