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+/*
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+ * arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
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+ *
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+ * Copyright (C) 2005 Paul Mundt
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+ *
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+ * TMU handling code hacked out of arch/sh/kernel/time.c
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+ *
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+ * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
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+ * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
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+ * Copyright (C) 2002, 2003, 2004 Paul Mundt
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+ * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
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+ *
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ */
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+#include <linux/init.h>
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+#include <linux/kernel.h>
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+#include <linux/interrupt.h>
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+#include <linux/spinlock.h>
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+#include <linux/seqlock.h>
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+#include <asm/timer.h>
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+#include <asm/rtc.h>
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+#include <asm/io.h>
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+#include <asm/irq.h>
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+#include <asm/clock.h>
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+
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+#define TMU_TOCR_INIT 0x00
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+#define TMU0_TCR_INIT 0x0020
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+#define TMU_TSTR_INIT 1
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+
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+#define TMU0_TCR_CALIB 0x0000
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+
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+static DEFINE_SPINLOCK(tmu0_lock);
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+
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+static unsigned long tmu_timer_get_offset(void)
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+{
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+ int count;
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+ unsigned long flags;
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+
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+ static int count_p = 0x7fffffff; /* for the first call after boot */
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+ static unsigned long jiffies_p = 0;
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+
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+ /*
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+ * cache volatile jiffies temporarily; we have IRQs turned off.
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+ */
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+ unsigned long jiffies_t;
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+
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+ spin_lock_irqsave(&tmu0_lock, flags);
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+ /* timer count may underflow right here */
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+ count = ctrl_inl(TMU0_TCNT); /* read the latched count */
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+
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+ jiffies_t = jiffies;
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+
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+ /*
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+ * avoiding timer inconsistencies (they are rare, but they happen)...
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+ * there is one kind of problem that must be avoided here:
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+ * 1. the timer counter underflows
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+ */
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+
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+ if (jiffies_t == jiffies_p) {
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+ if (count > count_p) {
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+ /* the nutcase */
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+ if (ctrl_inw(TMU0_TCR) & 0x100) { /* Check UNF bit */
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+ count -= LATCH;
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+ } else {
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+ printk("%s (): hardware timer problem?\n",
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+ __FUNCTION__);
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+ }
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+ }
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+ } else
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+ jiffies_p = jiffies_t;
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+
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+ count_p = count;
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+ spin_unlock_irqrestore(&tmu0_lock, flags);
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+
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+ count = ((LATCH-1) - count) * TICK_SIZE;
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+ count = (count + LATCH/2) / LATCH;
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+
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+ return count;
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+}
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+
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+static irqreturn_t tmu_timer_interrupt(int irq, void *dev_id,
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+ struct pt_regs *regs)
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+{
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+ unsigned long timer_status;
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+
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+ /* Clear UNF bit */
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+ timer_status = ctrl_inw(TMU0_TCR);
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+ timer_status &= ~0x100;
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+ ctrl_outw(timer_status, TMU0_TCR);
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+
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+ /*
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+ * Here we are in the timer irq handler. We just have irqs locally
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+ * disabled but we don't know if the timer_bh is running on the other
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+ * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
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+ * the irq version of write_lock because as just said we have irq
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+ * locally disabled. -arca
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+ */
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+ write_seqlock(&xtime_lock);
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+ handle_timer_tick(regs);
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+ write_sequnlock(&xtime_lock);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static struct irqaction tmu_irq = {
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+ .name = "timer",
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+ .handler = tmu_timer_interrupt,
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+ .flags = SA_INTERRUPT,
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+ .mask = CPU_MASK_NONE,
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+};
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+
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+/*
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+ * Hah! We'll see if this works (switching from usecs to nsecs).
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+ */
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+static unsigned long tmu_timer_get_frequency(void)
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+{
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+ u32 freq;
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+ struct timespec ts1, ts2;
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+ unsigned long diff_nsec;
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+ unsigned long factor;
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+
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+ /* Setup the timer: We don't want to generate interrupts, just
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+ * have it count down at its natural rate.
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+ */
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+ ctrl_outb(0, TMU_TSTR);
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+#if !defined(CONFIG_CPU_SUBTYPE_SH7300) && !defined(CONFIG_CPU_SUBTYPE_SH7760)
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+ ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
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+#endif
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+ ctrl_outw(TMU0_TCR_CALIB, TMU0_TCR);
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+ ctrl_outl(0xffffffff, TMU0_TCOR);
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+ ctrl_outl(0xffffffff, TMU0_TCNT);
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+
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+ rtc_get_time(&ts2);
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+
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+ do {
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+ rtc_get_time(&ts1);
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+ } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
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+
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+ /* actually start the timer */
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+ ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
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+
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+ do {
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+ rtc_get_time(&ts2);
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+ } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
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+
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+ freq = 0xffffffff - ctrl_inl(TMU0_TCNT);
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+ if (ts2.tv_nsec < ts1.tv_nsec) {
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+ ts2.tv_nsec += 1000000000;
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+ ts2.tv_sec--;
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+ }
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+
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+ diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
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+
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+ /* this should work well if the RTC has a precision of n Hz, where
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+ * n is an integer. I don't think we have to worry about the other
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+ * cases. */
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+ factor = (1000000000 + diff_nsec/2) / diff_nsec;
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+
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+ if (factor * diff_nsec > 1100000000 ||
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+ factor * diff_nsec < 900000000)
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+ panic("weird RTC (diff_nsec %ld)", diff_nsec);
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+
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+ return freq * factor;
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+}
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+
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+static void tmu_clk_init(struct clk *clk)
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+{
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+ u8 divisor = TMU0_TCR_INIT & 0x7;
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+ ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
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+ clk->rate = clk->parent->rate / (4 << (divisor << 1));
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+}
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+
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+static void tmu_clk_recalc(struct clk *clk)
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+{
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+ u8 divisor = ctrl_inw(TMU0_TCR) & 0x7;
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+ clk->rate = clk->parent->rate / (4 << (divisor << 1));
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+}
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+
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+static struct clk_ops tmu_clk_ops = {
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+ .init = tmu_clk_init,
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+ .recalc = tmu_clk_recalc,
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+};
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+
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+static struct clk tmu0_clk = {
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+ .name = "tmu0_clk",
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+ .ops = &tmu_clk_ops,
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+};
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+
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+static int tmu_timer_init(void)
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+{
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+ unsigned long interval;
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+
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+ setup_irq(TIMER_IRQ, &tmu_irq);
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+
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+ tmu0_clk.parent = clk_get("module_clk");
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+
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+ /* Start TMU0 */
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+ ctrl_outb(0, TMU_TSTR);
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+#if !defined(CONFIG_CPU_SUBTYPE_SH7300) && !defined(CONFIG_CPU_SUBTYPE_SH7760)
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+ ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
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+#endif
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+
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+ clk_register(&tmu0_clk);
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+ clk_enable(&tmu0_clk);
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+
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+ interval = (clk_get_rate(&tmu0_clk) + HZ / 2) / HZ;
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+ printk(KERN_INFO "Interval = %ld\n", interval);
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+
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+ ctrl_outl(interval, TMU0_TCOR);
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+ ctrl_outl(interval, TMU0_TCNT);
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+
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+ ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
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+
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+ return 0;
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+}
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+
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+struct sys_timer_ops tmu_timer_ops = {
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+ .init = tmu_timer_init,
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+ .get_frequency = tmu_timer_get_frequency,
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+ .get_offset = tmu_timer_get_offset,
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+};
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+
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+struct sys_timer tmu_timer = {
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+ .name = "tmu",
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+ .ops = &tmu_timer_ops,
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+};
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+
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