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@@ -203,7 +203,7 @@ ENTRY(secondary_startup_64)
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* addresses where we're currently running on. We have to do that here
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* because in 32bit we couldn't load a 64bit linear address.
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*/
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- lgdt cpu_gdt_descr(%rip)
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+ lgdt early_gdt_descr(%rip)
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/* set up data segments. actually 0 would do too */
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movl $__KERNEL_DS,%eax
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@@ -391,54 +391,16 @@ NEXT_PAGE(level2_spare_pgt)
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.data
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.align 16
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- .globl cpu_gdt_descr
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-cpu_gdt_descr:
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- .word gdt_end-cpu_gdt_table-1
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-gdt:
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- .quad cpu_gdt_table
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-#ifdef CONFIG_SMP
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- .rept NR_CPUS-1
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- .word 0
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- .quad 0
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- .endr
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-#endif
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+ .globl early_gdt_descr
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+early_gdt_descr:
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+ .word GDT_ENTRIES*8-1
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+ .quad per_cpu__gdt_page
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ENTRY(phys_base)
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/* This must match the first entry in level2_kernel_pgt */
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.quad 0x0000000000000000
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-/* We need valid kernel segments for data and code in long mode too
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- * IRET will check the segment types kkeil 2000/10/28
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- * Also sysret mandates a special GDT layout
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- */
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-
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- .section .data.page_aligned, "aw"
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- .align PAGE_SIZE
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-
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-/* The TLS descriptors are currently at a different place compared to i386.
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- Hopefully nobody expects them at a fixed place (Wine?) */
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-ENTRY(cpu_gdt_table)
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- .quad 0x0000000000000000 /* NULL descriptor */
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- .quad 0x00cf9b000000ffff /* __KERNEL32_CS */
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- .quad 0x00af9b000000ffff /* __KERNEL_CS */
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- .quad 0x00cf93000000ffff /* __KERNEL_DS */
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- .quad 0x00cffb000000ffff /* __USER32_CS */
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- .quad 0x00cff3000000ffff /* __USER_DS, __USER32_DS */
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- .quad 0x00affb000000ffff /* __USER_CS */
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- .quad 0x0 /* unused */
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- .quad 0,0 /* TSS */
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- .quad 0,0 /* LDT */
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- .quad 0,0,0 /* three TLS descriptors */
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- .quad 0x0000f40000000000 /* node/CPU stored in limit */
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-gdt_end:
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- /* asm/segment.h:GDT_ENTRIES must match this */
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- /* This should be a multiple of the cache line size */
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- /* GDTs of other CPUs are now dynamically allocated */
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-
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- /* zero the remaining page */
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- .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
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-
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.section .bss, "aw", @nobits
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.align L1_CACHE_BYTES
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ENTRY(idt_table)
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