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@@ -22,8 +22,10 @@
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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+#include <linux/pinctrl/pinconf-generic.h>
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#include "core.h"
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+#include "pinconf.h"
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#define DRIVER_NAME "pinctrl-single"
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#define PCS_MUX_PINS_NAME "pinctrl-single,pins"
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@@ -58,6 +60,33 @@ struct pcs_func_vals {
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unsigned mask;
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};
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+/**
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+ * struct pcs_conf_vals - pinconf parameter, pinconf register offset
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+ * and value, enable, disable, mask
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+ * @param: config parameter
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+ * @val: user input bits in the pinconf register
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+ * @enable: enable bits in the pinconf register
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+ * @disable: disable bits in the pinconf register
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+ * @mask: mask bits in the register value
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+ */
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+struct pcs_conf_vals {
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+ enum pin_config_param param;
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+ unsigned val;
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+ unsigned enable;
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+ unsigned disable;
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+ unsigned mask;
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+};
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+
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+/**
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+ * struct pcs_conf_type - pinconf property name, pinconf param pair
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+ * @name: property name in DTS file
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+ * @param: config parameter
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+ */
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+struct pcs_conf_type {
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+ const char *name;
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+ enum pin_config_param param;
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+};
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+
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/**
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* struct pcs_function - pinctrl function
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* @name: pinctrl function name
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@@ -73,6 +102,22 @@ struct pcs_function {
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unsigned nvals;
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const char **pgnames;
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int npgnames;
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+ struct pcs_conf_vals *conf;
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+ int nconfs;
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+ struct list_head node;
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+};
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+
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+/**
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+ * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
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+ * @offset: offset base of pins
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+ * @npins: number pins with the same mux value of gpio function
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+ * @gpiofunc: mux value of gpio function
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+ * @node: list node
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+ */
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+struct pcs_gpiofunc_range {
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+ unsigned offset;
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+ unsigned npins;
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+ unsigned gpiofunc;
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struct list_head node;
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};
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@@ -117,12 +162,14 @@ struct pcs_name {
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* @fshift: function register shift
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* @foff: value to turn mux off
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* @fmax: max number of functions in fmask
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+ * @is_pinconf: whether supports pinconf
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* @names: array of register names for pins
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* @pins: physical pins on the SoC
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* @pgtree: pingroup index radix tree
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* @ftree: function index radix tree
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* @pingroups: list of pingroups
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* @functions: list of functions
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+ * @gpiofuncs: list of gpio functions
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* @ngroups: number of pingroups
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* @nfuncs: number of functions
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* @desc: pin controller descriptor
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@@ -142,12 +189,14 @@ struct pcs_device {
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unsigned foff;
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unsigned fmax;
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bool bits_per_mux;
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+ bool is_pinconf;
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struct pcs_name *names;
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struct pcs_data pins;
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struct radix_tree_root pgtree;
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struct radix_tree_root ftree;
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struct list_head pingroups;
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struct list_head functions;
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+ struct list_head gpiofuncs;
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unsigned ngroups;
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unsigned nfuncs;
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struct pinctrl_desc desc;
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@@ -155,6 +204,16 @@ struct pcs_device {
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void (*write)(unsigned val, void __iomem *reg);
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};
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+static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
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+ unsigned long *config);
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+static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
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+ unsigned long config);
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+
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+static enum pin_config_param pcs_bias[] = {
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+ PIN_CONFIG_BIAS_PULL_DOWN,
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+ PIN_CONFIG_BIAS_PULL_UP,
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+};
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+
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/*
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* REVISIT: Reads and writes could eventually use regmap or something
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* generic. But at least on omaps, some mux registers are performance
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@@ -270,7 +329,7 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np_config,
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struct pinctrl_map **map, unsigned *num_maps);
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-static struct pinctrl_ops pcs_pinctrl_ops = {
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+static const struct pinctrl_ops pcs_pinctrl_ops = {
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.get_groups_count = pcs_get_groups_count,
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.get_group_name = pcs_get_group_name,
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.get_group_pins = pcs_get_group_pins,
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@@ -326,6 +385,28 @@ static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
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return 0;
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}
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+static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
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+ struct pcs_function **func)
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+{
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+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
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+ struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
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+ const struct pinctrl_setting_mux *setting;
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+ unsigned fselector;
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+
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+ /* If pin is not described in DTS & enabled, mux_setting is NULL. */
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+ setting = pdesc->mux_setting;
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+ if (!setting)
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+ return -ENOTSUPP;
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+ fselector = setting->func;
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+ *func = radix_tree_lookup(&pcs->ftree, fselector);
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+ if (!(*func)) {
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+ dev_err(pcs->dev, "%s could not find function%i\n",
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+ __func__, fselector);
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+ return -ENOTSUPP;
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+ }
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+ return 0;
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+}
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+
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static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
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unsigned group)
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{
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@@ -334,6 +415,9 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
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int i;
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pcs = pinctrl_dev_get_drvdata(pctldev);
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+ /* If function mask is null, needn't enable it. */
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+ if (!pcs->fmask)
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+ return 0;
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func = radix_tree_lookup(&pcs->ftree, fselector);
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if (!func)
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return -EINVAL;
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@@ -368,6 +452,10 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
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int i;
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pcs = pinctrl_dev_get_drvdata(pctldev);
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+ /* If function mask is null, needn't disable it. */
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+ if (!pcs->fmask)
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+ return;
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+
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func = radix_tree_lookup(&pcs->ftree, fselector);
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if (!func) {
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dev_err(pcs->dev, "%s could not find function%i\n",
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@@ -403,12 +491,33 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
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}
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static int pcs_request_gpio(struct pinctrl_dev *pctldev,
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- struct pinctrl_gpio_range *range, unsigned offset)
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+ struct pinctrl_gpio_range *range, unsigned pin)
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{
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- return -ENOTSUPP;
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+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
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+ struct pcs_gpiofunc_range *frange = NULL;
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+ struct list_head *pos, *tmp;
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+ int mux_bytes = 0;
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+ unsigned data;
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+
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+ /* If function mask is null, return directly. */
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+ if (!pcs->fmask)
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+ return -ENOTSUPP;
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+
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+ list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
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+ frange = list_entry(pos, struct pcs_gpiofunc_range, node);
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+ if (pin >= frange->offset + frange->npins
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+ || pin < frange->offset)
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+ continue;
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+ mux_bytes = pcs->width / BITS_PER_BYTE;
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+ data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
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+ data |= frange->gpiofunc;
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+ pcs->write(data, pcs->base + pin * mux_bytes);
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+ break;
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+ }
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+ return 0;
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}
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-static struct pinmux_ops pcs_pinmux_ops = {
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+static const struct pinmux_ops pcs_pinmux_ops = {
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.get_functions_count = pcs_get_functions_count,
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.get_function_name = pcs_get_function_name,
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.get_function_groups = pcs_get_function_groups,
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@@ -417,32 +526,191 @@ static struct pinmux_ops pcs_pinmux_ops = {
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.gpio_request_enable = pcs_request_gpio,
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};
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+/* Clear BIAS value */
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+static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
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+{
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+ unsigned long config;
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+ int i;
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+ for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
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+ config = pinconf_to_config_packed(pcs_bias[i], 0);
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+ pcs_pinconf_set(pctldev, pin, config);
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+ }
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+}
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+
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+/*
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+ * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
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+ * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
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+ */
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+static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
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+{
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+ unsigned long config;
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
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+ config = pinconf_to_config_packed(pcs_bias[i], 0);
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+ if (!pcs_pinconf_get(pctldev, pin, &config))
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+ goto out;
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+ }
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+ return true;
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+out:
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+ return false;
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+}
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+
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static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned pin, unsigned long *config)
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{
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+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
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+ struct pcs_function *func;
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+ enum pin_config_param param;
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+ unsigned offset = 0, data = 0, i, j, ret;
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+
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+ ret = pcs_get_function(pctldev, pin, &func);
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+ if (ret)
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+ return ret;
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+
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+ for (i = 0; i < func->nconfs; i++) {
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+ param = pinconf_to_config_param(*config);
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+ if (param == PIN_CONFIG_BIAS_DISABLE) {
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+ if (pcs_pinconf_bias_disable(pctldev, pin)) {
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+ *config = 0;
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+ return 0;
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+ } else {
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+ return -ENOTSUPP;
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+ }
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+ } else if (param != func->conf[i].param) {
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+ continue;
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+ }
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+
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+ offset = pin * (pcs->width / BITS_PER_BYTE);
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+ data = pcs->read(pcs->base + offset) & func->conf[i].mask;
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+ switch (func->conf[i].param) {
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+ /* 4 parameters */
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+ case PIN_CONFIG_BIAS_PULL_DOWN:
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+ case PIN_CONFIG_BIAS_PULL_UP:
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+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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+ if ((data != func->conf[i].enable) ||
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+ (data == func->conf[i].disable))
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+ return -ENOTSUPP;
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+ *config = 0;
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+ break;
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+ /* 2 parameters */
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+ case PIN_CONFIG_INPUT_SCHMITT:
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+ for (j = 0; j < func->nconfs; j++) {
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+ switch (func->conf[j].param) {
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+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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+ if (data != func->conf[j].enable)
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+ return -ENOTSUPP;
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+ break;
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+ default:
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+ break;
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+ }
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+ }
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+ *config = data;
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+ break;
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+ case PIN_CONFIG_DRIVE_STRENGTH:
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+ case PIN_CONFIG_SLEW_RATE:
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+ default:
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+ *config = data;
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+ break;
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+ }
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+ return 0;
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+ }
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return -ENOTSUPP;
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}
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static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
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unsigned pin, unsigned long config)
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{
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+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
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+ struct pcs_function *func;
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+ unsigned offset = 0, shift = 0, arg = 0, i, data, ret;
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+ u16 argument;
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+
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+ ret = pcs_get_function(pctldev, pin, &func);
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+ if (ret)
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+ return ret;
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+
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+ for (i = 0; i < func->nconfs; i++) {
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+ if (pinconf_to_config_param(config) == func->conf[i].param) {
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+ offset = pin * (pcs->width / BITS_PER_BYTE);
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+ data = pcs->read(pcs->base + offset);
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+ argument = pinconf_to_config_argument(config);
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+ switch (func->conf[i].param) {
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+ /* 2 parameters */
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+ case PIN_CONFIG_INPUT_SCHMITT:
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+ case PIN_CONFIG_DRIVE_STRENGTH:
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+ case PIN_CONFIG_SLEW_RATE:
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+ shift = ffs(func->conf[i].mask) - 1;
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+ arg = pinconf_to_config_argument(config);
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+ data &= ~func->conf[i].mask;
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+ data |= (arg << shift) & func->conf[i].mask;
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+ break;
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+ /* 4 parameters */
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+ case PIN_CONFIG_BIAS_DISABLE:
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+ pcs_pinconf_clear_bias(pctldev, pin);
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+ break;
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+ case PIN_CONFIG_BIAS_PULL_DOWN:
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+ case PIN_CONFIG_BIAS_PULL_UP:
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+ if (argument)
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+ pcs_pinconf_clear_bias(pctldev, pin);
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+ /* fall through */
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+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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+ data &= ~func->conf[i].mask;
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+ if (argument)
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+ data |= func->conf[i].enable;
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+ else
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+ data |= func->conf[i].disable;
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+ break;
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+ default:
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+ return -ENOTSUPP;
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+ }
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+ pcs->write(data, pcs->base + offset);
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+ return 0;
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+ }
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+ }
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return -ENOTSUPP;
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}
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static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
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unsigned group, unsigned long *config)
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{
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- return -ENOTSUPP;
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+ const unsigned *pins;
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+ unsigned npins, old = 0;
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+ int i, ret;
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+
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+ ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
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+ if (ret)
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+ return ret;
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+ for (i = 0; i < npins; i++) {
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+ if (pcs_pinconf_get(pctldev, pins[i], config))
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+ return -ENOTSUPP;
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+ /* configs do not match between two pins */
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+ if (i && (old != *config))
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+ return -ENOTSUPP;
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+ old = *config;
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+ }
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+ return 0;
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}
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static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
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unsigned group, unsigned long config)
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{
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- return -ENOTSUPP;
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+ const unsigned *pins;
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+ unsigned npins;
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+ int i, ret;
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+
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+ ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
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+ if (ret)
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+ return ret;
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+ for (i = 0; i < npins; i++) {
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+ if (pcs_pinconf_set(pctldev, pins[i], config))
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+ return -ENOTSUPP;
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+ }
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+ return 0;
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}
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static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
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- struct seq_file *s, unsigned offset)
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+ struct seq_file *s, unsigned pin)
|
|
|
{
|
|
|
}
|
|
|
|
|
|
@@ -451,13 +719,22 @@ static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
|
|
|
{
|
|
|
}
|
|
|
|
|
|
-static struct pinconf_ops pcs_pinconf_ops = {
|
|
|
+static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
|
|
|
+ struct seq_file *s,
|
|
|
+ unsigned long config)
|
|
|
+{
|
|
|
+ pinconf_generic_dump_config(pctldev, s, config);
|
|
|
+}
|
|
|
+
|
|
|
+static const struct pinconf_ops pcs_pinconf_ops = {
|
|
|
.pin_config_get = pcs_pinconf_get,
|
|
|
.pin_config_set = pcs_pinconf_set,
|
|
|
.pin_config_group_get = pcs_pinconf_group_get,
|
|
|
.pin_config_group_set = pcs_pinconf_group_set,
|
|
|
.pin_config_dbg_show = pcs_pinconf_dbg_show,
|
|
|
.pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
|
|
|
+ .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
|
|
|
+ .is_generic = true,
|
|
|
};
|
|
|
|
|
|
/**
|
|
|
@@ -648,11 +925,157 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
|
|
|
return index;
|
|
|
}
|
|
|
|
|
|
+/*
|
|
|
+ * check whether data matches enable bits or disable bits
|
|
|
+ * Return value: 1 for matching enable bits, 0 for matching disable bits,
|
|
|
+ * and negative value for matching failure.
|
|
|
+ */
|
|
|
+static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
|
|
|
+{
|
|
|
+ int ret = -EINVAL;
|
|
|
+
|
|
|
+ if (data == enable)
|
|
|
+ ret = 1;
|
|
|
+ else if (data == disable)
|
|
|
+ ret = 0;
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
|
|
|
+ unsigned value, unsigned enable, unsigned disable,
|
|
|
+ unsigned mask)
|
|
|
+{
|
|
|
+ (*conf)->param = param;
|
|
|
+ (*conf)->val = value;
|
|
|
+ (*conf)->enable = enable;
|
|
|
+ (*conf)->disable = disable;
|
|
|
+ (*conf)->mask = mask;
|
|
|
+ (*conf)++;
|
|
|
+}
|
|
|
+
|
|
|
+static void add_setting(unsigned long **setting, enum pin_config_param param,
|
|
|
+ unsigned arg)
|
|
|
+{
|
|
|
+ **setting = pinconf_to_config_packed(param, arg);
|
|
|
+ (*setting)++;
|
|
|
+}
|
|
|
+
|
|
|
+/* add pinconf setting with 2 parameters */
|
|
|
+static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
|
|
|
+ const char *name, enum pin_config_param param,
|
|
|
+ struct pcs_conf_vals **conf, unsigned long **settings)
|
|
|
+{
|
|
|
+ unsigned value[2];
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ ret = of_property_read_u32_array(np, name, value, 2);
|
|
|
+ if (ret)
|
|
|
+ return;
|
|
|
+ /* set value & mask */
|
|
|
+ value[0] &= value[1];
|
|
|
+ /* skip enable & disable */
|
|
|
+ add_config(conf, param, value[0], 0, 0, value[1]);
|
|
|
+ add_setting(settings, param, value[0]);
|
|
|
+}
|
|
|
+
|
|
|
+/* add pinconf setting with 4 parameters */
|
|
|
+static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
|
|
|
+ const char *name, enum pin_config_param param,
|
|
|
+ struct pcs_conf_vals **conf, unsigned long **settings)
|
|
|
+{
|
|
|
+ unsigned value[4];
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ /* value to set, enable, disable, mask */
|
|
|
+ ret = of_property_read_u32_array(np, name, value, 4);
|
|
|
+ if (ret)
|
|
|
+ return;
|
|
|
+ if (!value[3]) {
|
|
|
+ dev_err(pcs->dev, "mask field of the property can't be 0\n");
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ value[0] &= value[3];
|
|
|
+ value[1] &= value[3];
|
|
|
+ value[2] &= value[3];
|
|
|
+ ret = pcs_config_match(value[0], value[1], value[2]);
|
|
|
+ if (ret < 0)
|
|
|
+ dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
|
|
|
+ add_config(conf, param, value[0], value[1], value[2], value[3]);
|
|
|
+ add_setting(settings, param, ret);
|
|
|
+}
|
|
|
+
|
|
|
+static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
|
|
|
+ struct pcs_function *func,
|
|
|
+ struct pinctrl_map **map)
|
|
|
+
|
|
|
+{
|
|
|
+ struct pinctrl_map *m = *map;
|
|
|
+ int i = 0, nconfs = 0;
|
|
|
+ unsigned long *settings = NULL, *s = NULL;
|
|
|
+ struct pcs_conf_vals *conf = NULL;
|
|
|
+ struct pcs_conf_type prop2[] = {
|
|
|
+ { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
|
|
|
+ { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
|
|
|
+ { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
|
|
|
+ };
|
|
|
+ struct pcs_conf_type prop4[] = {
|
|
|
+ { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
|
|
|
+ { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
|
|
|
+ { "pinctrl-single,input-schmitt-enable",
|
|
|
+ PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
|
|
|
+ };
|
|
|
+
|
|
|
+ /* If pinconf isn't supported, don't parse properties in below. */
|
|
|
+ if (!pcs->is_pinconf)
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ /* cacluate how much properties are supported in current node */
|
|
|
+ for (i = 0; i < ARRAY_SIZE(prop2); i++) {
|
|
|
+ if (of_find_property(np, prop2[i].name, NULL))
|
|
|
+ nconfs++;
|
|
|
+ }
|
|
|
+ for (i = 0; i < ARRAY_SIZE(prop4); i++) {
|
|
|
+ if (of_find_property(np, prop4[i].name, NULL))
|
|
|
+ nconfs++;
|
|
|
+ }
|
|
|
+ if (!nconfs)
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ func->conf = devm_kzalloc(pcs->dev,
|
|
|
+ sizeof(struct pcs_conf_vals) * nconfs,
|
|
|
+ GFP_KERNEL);
|
|
|
+ if (!func->conf)
|
|
|
+ return -ENOMEM;
|
|
|
+ func->nconfs = nconfs;
|
|
|
+ conf = &(func->conf[0]);
|
|
|
+ m++;
|
|
|
+ settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
|
|
|
+ GFP_KERNEL);
|
|
|
+ if (!settings)
|
|
|
+ return -ENOMEM;
|
|
|
+ s = &settings[0];
|
|
|
+
|
|
|
+ for (i = 0; i < ARRAY_SIZE(prop2); i++)
|
|
|
+ pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
|
|
|
+ &conf, &s);
|
|
|
+ for (i = 0; i < ARRAY_SIZE(prop4); i++)
|
|
|
+ pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
|
|
|
+ &conf, &s);
|
|
|
+ m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
|
|
|
+ m->data.configs.group_or_pin = np->name;
|
|
|
+ m->data.configs.configs = settings;
|
|
|
+ m->data.configs.num_configs = nconfs;
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void pcs_free_pingroups(struct pcs_device *pcs);
|
|
|
+
|
|
|
/**
|
|
|
* smux_parse_one_pinctrl_entry() - parses a device tree mux entry
|
|
|
* @pcs: pinctrl driver instance
|
|
|
* @np: device node of the mux entry
|
|
|
* @map: map entry
|
|
|
+ * @num_maps: number of map
|
|
|
* @pgnames: pingroup names
|
|
|
*
|
|
|
* Note that this binding currently supports only sets of one register + value.
|
|
|
@@ -669,6 +1092,7 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
|
|
|
static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
|
|
|
struct device_node *np,
|
|
|
struct pinctrl_map **map,
|
|
|
+ unsigned *num_maps,
|
|
|
const char **pgnames)
|
|
|
{
|
|
|
struct pcs_func_vals *vals;
|
|
|
@@ -741,8 +1165,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
|
|
|
(*map)->data.mux.group = np->name;
|
|
|
(*map)->data.mux.function = np->name;
|
|
|
|
|
|
+ if (pcs->is_pinconf) {
|
|
|
+ if (pcs_parse_pinconf(pcs, np, function, map))
|
|
|
+ goto free_pingroups;
|
|
|
+ *num_maps = 2;
|
|
|
+ } else {
|
|
|
+ *num_maps = 1;
|
|
|
+ }
|
|
|
return 0;
|
|
|
|
|
|
+free_pingroups:
|
|
|
+ pcs_free_pingroups(pcs);
|
|
|
+ *num_maps = 1;
|
|
|
free_function:
|
|
|
pcs_remove_function(pcs, function);
|
|
|
|
|
|
@@ -771,7 +1205,8 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
|
|
|
|
|
|
pcs = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
|
|
- *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL);
|
|
|
+ /* create 2 maps. One is for pinmux, and the other is for pinconf. */
|
|
|
+ *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
|
|
|
if (!*map)
|
|
|
return -ENOMEM;
|
|
|
|
|
|
@@ -783,13 +1218,13 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
|
|
|
goto free_map;
|
|
|
}
|
|
|
|
|
|
- ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames);
|
|
|
+ ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps,
|
|
|
+ pgnames);
|
|
|
if (ret < 0) {
|
|
|
dev_err(pcs->dev, "no pins entries for %s\n",
|
|
|
np_config->name);
|
|
|
goto free_pgnames;
|
|
|
}
|
|
|
- *num_maps = 1;
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
@@ -879,6 +1314,37 @@ static void pcs_free_resources(struct pcs_device *pcs)
|
|
|
|
|
|
static struct of_device_id pcs_of_match[];
|
|
|
|
|
|
+static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
|
|
|
+{
|
|
|
+ const char *propname = "pinctrl-single,gpio-range";
|
|
|
+ const char *cellname = "#pinctrl-single,gpio-range-cells";
|
|
|
+ struct of_phandle_args gpiospec;
|
|
|
+ struct pcs_gpiofunc_range *range;
|
|
|
+ int ret, i;
|
|
|
+
|
|
|
+ for (i = 0; ; i++) {
|
|
|
+ ret = of_parse_phandle_with_args(node, propname, cellname,
|
|
|
+ i, &gpiospec);
|
|
|
+ /* Do not treat it as error. Only treat it as end condition. */
|
|
|
+ if (ret) {
|
|
|
+ ret = 0;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
|
|
|
+ if (!range) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ range->offset = gpiospec.args[0];
|
|
|
+ range->npins = gpiospec.args[1];
|
|
|
+ range->gpiofunc = gpiospec.args[2];
|
|
|
+ mutex_lock(&pcs->mutex);
|
|
|
+ list_add_tail(&range->node, &pcs->gpiofuncs);
|
|
|
+ mutex_unlock(&pcs->mutex);
|
|
|
+ }
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
static int pcs_probe(struct platform_device *pdev)
|
|
|
{
|
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
@@ -900,14 +1366,23 @@ static int pcs_probe(struct platform_device *pdev)
|
|
|
mutex_init(&pcs->mutex);
|
|
|
INIT_LIST_HEAD(&pcs->pingroups);
|
|
|
INIT_LIST_HEAD(&pcs->functions);
|
|
|
+ INIT_LIST_HEAD(&pcs->gpiofuncs);
|
|
|
+ pcs->is_pinconf = match->data;
|
|
|
|
|
|
PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
|
|
|
"register width not specified\n");
|
|
|
|
|
|
- PCS_GET_PROP_U32("pinctrl-single,function-mask", &pcs->fmask,
|
|
|
- "function register mask not specified\n");
|
|
|
- pcs->fshift = ffs(pcs->fmask) - 1;
|
|
|
- pcs->fmax = pcs->fmask >> pcs->fshift;
|
|
|
+ ret = of_property_read_u32(np, "pinctrl-single,function-mask",
|
|
|
+ &pcs->fmask);
|
|
|
+ if (!ret) {
|
|
|
+ pcs->fshift = ffs(pcs->fmask) - 1;
|
|
|
+ pcs->fmax = pcs->fmask >> pcs->fshift;
|
|
|
+ } else {
|
|
|
+ /* If mask property doesn't exist, function mux is invalid. */
|
|
|
+ pcs->fmask = 0;
|
|
|
+ pcs->fshift = 0;
|
|
|
+ pcs->fmax = 0;
|
|
|
+ }
|
|
|
|
|
|
ret = of_property_read_u32(np, "pinctrl-single,function-off",
|
|
|
&pcs->foff);
|
|
|
@@ -961,7 +1436,8 @@ static int pcs_probe(struct platform_device *pdev)
|
|
|
pcs->desc.name = DRIVER_NAME;
|
|
|
pcs->desc.pctlops = &pcs_pinctrl_ops;
|
|
|
pcs->desc.pmxops = &pcs_pinmux_ops;
|
|
|
- pcs->desc.confops = &pcs_pinconf_ops;
|
|
|
+ if (pcs->is_pinconf)
|
|
|
+ pcs->desc.confops = &pcs_pinconf_ops;
|
|
|
pcs->desc.owner = THIS_MODULE;
|
|
|
|
|
|
ret = pcs_allocate_pin_table(pcs);
|
|
|
@@ -975,6 +1451,10 @@ static int pcs_probe(struct platform_device *pdev)
|
|
|
goto free;
|
|
|
}
|
|
|
|
|
|
+ ret = pcs_add_gpio_func(np, pcs);
|
|
|
+ if (ret < 0)
|
|
|
+ goto free;
|
|
|
+
|
|
|
dev_info(pcs->dev, "%i pins at pa %p size %u\n",
|
|
|
pcs->desc.npins, pcs->base, pcs->size);
|
|
|
|
|
|
@@ -999,7 +1479,8 @@ static int pcs_remove(struct platform_device *pdev)
|
|
|
}
|
|
|
|
|
|
static struct of_device_id pcs_of_match[] = {
|
|
|
- { .compatible = DRIVER_NAME, },
|
|
|
+ { .compatible = "pinctrl-single", .data = (void *)false },
|
|
|
+ { .compatible = "pinconf-single", .data = (void *)true },
|
|
|
{ },
|
|
|
};
|
|
|
MODULE_DEVICE_TABLE(of, pcs_of_match);
|
Simon Horman