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@@ -3117,13 +3117,12 @@ static void dispc_dump_regs(struct seq_file *s)
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}
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static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
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- bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
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- u8 acb)
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+ bool rf, bool ieo, bool ipc, bool ihs, bool ivs)
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{
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u32 l = 0;
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- DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
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- onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
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+ DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d\n",
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+ onoff, rf, ieo, ipc, ihs, ivs);
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l |= FLD_VAL(onoff, 17, 17);
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l |= FLD_VAL(rf, 16, 16);
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@@ -3131,22 +3130,19 @@ static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
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l |= FLD_VAL(ipc, 14, 14);
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l |= FLD_VAL(ihs, 13, 13);
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l |= FLD_VAL(ivs, 12, 12);
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- l |= FLD_VAL(acbi, 11, 8);
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- l |= FLD_VAL(acb, 7, 0);
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dispc_write_reg(DISPC_POL_FREQ(channel), l);
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}
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void dispc_mgr_set_pol_freq(enum omap_channel channel,
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- enum omap_panel_config config, u8 acbi, u8 acb)
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+ enum omap_panel_config config)
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{
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_dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
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(config & OMAP_DSS_LCD_RF) != 0,
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(config & OMAP_DSS_LCD_IEO) != 0,
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(config & OMAP_DSS_LCD_IPC) != 0,
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(config & OMAP_DSS_LCD_IHS) != 0,
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- (config & OMAP_DSS_LCD_IVS) != 0,
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- acbi, acb);
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+ (config & OMAP_DSS_LCD_IVS) != 0);
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}
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/* with fck as input clock rate, find dispc dividers that produce req_pck */
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