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@@ -121,6 +121,8 @@ static int __init pxa_init_gpio_chip(int gpio_end)
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return -ENOMEM;
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}
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+ memset(chips, 0, nbanks * sizeof(struct pxa_gpio_chip));
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+
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for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
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struct gpio_chip *c = &chips[i].chip;
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@@ -143,6 +145,21 @@ static int __init pxa_init_gpio_chip(int gpio_end)
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return 0;
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}
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+/* Update only those GRERx and GFERx edge detection register bits if those
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+ * bits are set in c->irq_mask
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+ */
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+static inline void update_edge_detect(struct pxa_gpio_chip *c)
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+{
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+ uint32_t grer, gfer;
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+
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+ grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask;
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+ gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask;
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+ grer |= c->irq_edge_rise & c->irq_mask;
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+ gfer |= c->irq_edge_fall & c->irq_mask;
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+ __raw_writel(grer, c->regbase + GRER_OFFSET);
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+ __raw_writel(gfer, c->regbase + GFER_OFFSET);
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+}
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+
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static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
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{
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struct pxa_gpio_chip *c;
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@@ -181,8 +198,7 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
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else
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c->irq_edge_fall &= ~mask;
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- __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET);
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- __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET);
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+ update_edge_detect(c);
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pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
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((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
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@@ -244,8 +260,7 @@ static void pxa_unmask_muxed_gpio(unsigned int irq)
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struct pxa_gpio_chip *c = gpio_to_chip(gpio);
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c->irq_mask |= GPIO_bit(gpio);
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- __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET);
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- __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET);
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+ update_edge_detect(c);
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}
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static struct irq_chip pxa_muxed_gpio_chip = {
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