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@@ -55,7 +55,8 @@ enum timer_location {
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#if defined(CONFIG_ARCH_QSD8X50)
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#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
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#define MSM_DGT_SHIFT (0)
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-#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
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+#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
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+ defined(CONFIG_ARCH_MSM8960)
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#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
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#define MSM_DGT_SHIFT (0)
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#else
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@@ -214,7 +215,7 @@ static void __init msm_timer_init(void)
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} else if (cpu_is_qsd8x50()) {
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msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
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msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
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- } else if (cpu_is_msm8x60()) {
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+ } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
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msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
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msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
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