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@@ -49,7 +49,7 @@
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#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
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#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
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-#define DMAR_OPERATION_TIMEOUT (HZ*60) /* 1m */
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+#define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) /* 10sec */
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#define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
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#define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
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@@ -490,12 +490,12 @@ static int iommu_alloc_root_entry(struct intel_iommu *iommu)
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#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
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#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
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{\
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{\
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- unsigned long start_time = jiffies;\
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+ cycles_t start_time = get_cycles();\
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while (1) {\
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while (1) {\
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sts = op (iommu->reg + offset);\
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sts = op (iommu->reg + offset);\
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if (cond)\
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if (cond)\
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break;\
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break;\
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- if (time_after(jiffies, start_time + DMAR_OPERATION_TIMEOUT))\
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+ if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
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panic("DMAR hardware is malfunctioning\n");\
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panic("DMAR hardware is malfunctioning\n");\
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cpu_relax();\
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cpu_relax();\
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}\
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}\
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