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@@ -42,6 +42,15 @@
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V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \
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}
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+/* Note: these are the nominal timings, for HDMI links this format is typically
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+ * double-clocked to meet the minimum pixelclock requirements. */
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+#define V4L2_DV_BT_CEA_720X480I59_94 { \
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+ .type = V4L2_DV_BT_656_1120, \
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+ V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
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+ 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
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+ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
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+}
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+
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#define V4L2_DV_BT_CEA_720X480P59_94 { \
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.type = V4L2_DV_BT_656_1120, \
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V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
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@@ -49,6 +58,15 @@
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V4L2_DV_BT_STD_CEA861, 0) \
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}
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+/* Note: these are the nominal timings, for HDMI links this format is typically
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+ * double-clocked to meet the minimum pixelclock requirements. */
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+#define V4L2_DV_BT_CEA_720X576I50 { \
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+ .type = V4L2_DV_BT_656_1120, \
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+ V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
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+ 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
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+ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
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+}
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+
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#define V4L2_DV_BT_CEA_720X576P50 { \
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.type = V4L2_DV_BT_656_1120, \
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V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
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