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@@ -0,0 +1,383 @@
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+/*
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+ *
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+ * (C) Copyright 2003
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+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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+ *
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+ * (C) Copyright 2004 Red Hat, Inc.
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+ *
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+ * 2005 (c) MontaVista Software, Inc.
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+ * Vitaly Bordug <vbordug@ru.mvista.com>
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/pci.h>
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+#include <linux/slab.h>
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+#include <linux/delay.h>
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+#include <linux/irq.h>
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+#include <linux/interrupt.h>
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+
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+#include <asm/byteorder.h>
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+#include <asm/io.h>
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+#include <asm/irq.h>
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+#include <asm/uaccess.h>
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+#include <asm/machdep.h>
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+#include <asm/pci-bridge.h>
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+#include <asm/immap_cpm2.h>
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+#include <asm/mpc8260.h>
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+#include <asm/cpm2.h>
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+
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+#include "m82xx_pci.h"
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+
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+/*
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+ * Interrupt routing
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+ */
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+
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+static inline int
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+pq2pci_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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+{
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+ static char pci_irq_table[][4] =
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+ /*
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+ * PCI IDSEL/INTPIN->INTLINE
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+ * A B C D
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+ */
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+ {
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+ { PIRQA, PIRQB, PIRQC, PIRQD }, /* IDSEL 22 - PCI slot 0 */
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+ { PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI slot 1 */
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+ { PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI slot 2 */
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+ };
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+
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+ const long min_idsel = 22, max_idsel = 24, irqs_per_slot = 4;
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+ return PCI_IRQ_TABLE_LOOKUP;
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+}
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+
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+static void
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+pq2pci_mask_irq(unsigned int irq)
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+{
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+ int bit = irq - NR_CPM_INTS;
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+
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+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
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+ return;
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+}
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+
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+static void
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+pq2pci_unmask_irq(unsigned int irq)
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+{
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+ int bit = irq - NR_CPM_INTS;
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+
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+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
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+ return;
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+}
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+
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+static void
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+pq2pci_mask_and_ack(unsigned int irq)
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+{
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+ int bit = irq - NR_CPM_INTS;
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+
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+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
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+ return;
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+}
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+
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+static void
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+pq2pci_end_irq(unsigned int irq)
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+{
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+ int bit = irq - NR_CPM_INTS;
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+
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+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
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+ return;
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+}
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+
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+struct hw_interrupt_type pq2pci_ic = {
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+ "PQ2 PCI",
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+ NULL,
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+ NULL,
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+ pq2pci_unmask_irq,
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+ pq2pci_mask_irq,
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+ pq2pci_mask_and_ack,
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+ pq2pci_end_irq,
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+ 0
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+};
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+
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+static irqreturn_t
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+pq2pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
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+{
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+ unsigned long stat, mask, pend;
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+ int bit;
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+
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+ for(;;) {
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+ stat = *(volatile unsigned long *) PCI_INT_STAT_REG;
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+ mask = *(volatile unsigned long *) PCI_INT_MASK_REG;
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+ pend = stat & ~mask & 0xf0000000;
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+ if (!pend)
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+ break;
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+ for (bit = 0; pend != 0; ++bit, pend <<= 1) {
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+ if (pend & 0x80000000)
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+ __do_IRQ(NR_CPM_INTS + bit, regs);
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+ }
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+ }
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static struct irqaction pq2pci_irqaction = {
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+ .handler = pq2pci_irq_demux,
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+ .flags = SA_INTERRUPT,
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+ .mask = CPU_MASK_NONE,
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+ .name = "PQ2 PCI cascade",
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+};
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+
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+
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+void
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+pq2pci_init_irq(void)
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+{
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+ int irq;
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+ volatile cpm2_map_t *immap = cpm2_immr;
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+#if defined CONFIG_ADS8272
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+ /* configure chip select for PCI interrupt controller */
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+ immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
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+ immap->im_memctl.memc_or3 = 0xffff8010;
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+#elif defined CONFIG_PQ2FADS
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+ immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801;
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+ immap->im_memctl.memc_or8 = 0xffff8010;
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+#endif
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+ for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
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+ irq_desc[irq].handler = &pq2pci_ic;
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+
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+ /* make PCI IRQ level sensitive */
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+ immap->im_intctl.ic_siexr &=
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+ ~(1 << (14 - (PCI_INT_TO_SIU - SIU_INT_IRQ1)));
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+
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+ /* mask all PCI interrupts */
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+ *(volatile unsigned long *) PCI_INT_MASK_REG |= 0xfff00000;
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+
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+ /* install the demultiplexer for the PCI cascade interrupt */
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+ setup_irq(PCI_INT_TO_SIU, &pq2pci_irqaction);
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+ return;
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+}
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+
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+static int
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+pq2pci_exclude_device(u_char bus, u_char devfn)
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+{
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+/* PCI bus configuration registers.
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+ */
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+static void
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+pq2ads_setup_pci(struct pci_controller *hose)
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+{
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+ __u32 val;
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+ volatile cpm2_map_t *immap = cpm2_immr;
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+ bd_t* binfo = (bd_t*) __res;
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+ u32 sccr = immap->im_clkrst.car_sccr;
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+ uint pci_div,freq,time;
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+ /* PCI int lowest prio */
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+ /* Each 4 bits is a device bus request and the MS 4bits
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+ is highest priority */
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+ /* Bus 4bit value
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+ --- ----------
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+ CPM high 0b0000
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+ CPM middle 0b0001
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+ CPM low 0b0010
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+ PCI reguest 0b0011
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+ Reserved 0b0100
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+ Reserved 0b0101
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+ Internal Core 0b0110
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+ External Master 1 0b0111
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+ External Master 2 0b1000
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+ External Master 3 0b1001
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+ The rest are reserved
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+ */
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+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
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+ /* park bus on core */
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+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE;
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+ /*
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+ * Set up master windows that allow the CPU to access PCI space. These
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+ * windows are set up using the two SIU PCIBR registers.
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+ */
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+
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+ immap->im_memctl.memc_pcimsk0 = M82xx_PCI_PRIM_WND_SIZE;
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+ immap->im_memctl.memc_pcibr0 = M82xx_PCI_PRIM_WND_BASE | PCIBR_ENABLE;
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+
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+#ifdef M82xx_PCI_SEC_WND_SIZE
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+ immap->im_memctl.memc_pcimsk1 = M82xx_PCI_SEC_WND_SIZE;
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+ immap->im_memctl.memc_pcibr1 = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE;
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+#endif
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+
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+#if defined CONFIG_ADS8272
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+ immap->im_siu_conf.siu_82xx.sc_siumcr =
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+ (immap->im_siu_conf.siu_82xx.sc_siumcr &
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+ ~(SIUMCR_BBD | SIUMCR_ESE | SIUMCR_PBSE |
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+ SIUMCR_CDIS | SIUMCR_DPPC11 | SIUMCR_L2CPC11 |
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+ SIUMCR_LBPC11 | SIUMCR_APPC11 |
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+ SIUMCR_CS10PC11 | SIUMCR_BCTLC11 | SIUMCR_MMR11)) |
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+ SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 |
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+ SIUMCR_APPC10 | SIUMCR_CS10PC00 |
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+ SIUMCR_BCTLC00 | SIUMCR_MMR11 ;
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+
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+#elif defined CONFIG_PQ2FADS
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+ /*
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+ * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
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+ * and local bus for PCI (SIUMCR [LBPC]).
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+ */
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+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
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+ ~(SIUMCR_L2PC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
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+ SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10;
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+#endif
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+ /* Enable PCI */
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+ immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
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+
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+ pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
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+ ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
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+ freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div));
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+ time = (int)666666/freq;
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+ /* due to PCI Local Bus spec, some devices needs to wait such a long
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+ time after RST deassertion. More specifically, 0.508s for 66MHz & twice more for 33 */
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+ printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting RST...\n",__FILE__,freq,
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+ (time==1) ? "0.5 seconds":"1 second" );
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+
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+ {
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+ int i;
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+ for(i=0;i<(500*time);i++)
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+ udelay(1000);
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+ }
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+
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+ /* setup ATU registers */
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+ immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO |
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+ ((~(M82xx_PCI_IO_SIZE - 1U)) >> POTA_ADDR_SHIFT));
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+ immap->im_pci.pci_potar0 = cpu_to_le32(M82xx_PCI_LOWER_IO >> POTA_ADDR_SHIFT);
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+ immap->im_pci.pci_pobar0 = cpu_to_le32(M82xx_PCI_IO_BASE >> POTA_ADDR_SHIFT);
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+
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+ /* Set-up non-prefetchable window */
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+ immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | ((~(M82xx_PCI_MMIO_SIZE-1U)) >> POTA_ADDR_SHIFT));
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+ immap->im_pci.pci_potar1 = cpu_to_le32(M82xx_PCI_LOWER_MMIO >> POTA_ADDR_SHIFT);
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+ immap->im_pci.pci_pobar1 = cpu_to_le32((M82xx_PCI_LOWER_MMIO - M82xx_PCI_MMIO_OFFSET) >> POTA_ADDR_SHIFT);
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+
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+ /* Set-up prefetchable window */
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+ immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN |
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+ (~(M82xx_PCI_MEM_SIZE-1U) >> POTA_ADDR_SHIFT));
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+ immap->im_pci.pci_potar2 = cpu_to_le32(M82xx_PCI_LOWER_MEM >> POTA_ADDR_SHIFT);
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+ immap->im_pci.pci_pobar2 = cpu_to_le32((M82xx_PCI_LOWER_MEM - M82xx_PCI_MEM_OFFSET) >> POTA_ADDR_SHIFT);
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+
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+ /* Inbound transactions from PCI memory space */
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+ immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN |
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+ ((~(M82xx_PCI_SLAVE_MEM_SIZE-1U)) >> PITA_ADDR_SHIFT));
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+ immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS >> PITA_ADDR_SHIFT);
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+ immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT);
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+
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+#if defined CONFIG_ADS8272
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+ /* PCI int highest prio */
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+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
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+#elif defined CONFIG_PQ2FADS
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+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
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+#endif
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+ /* park bus on PCI */
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+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
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+
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+ /* Enable bus mastering and inbound memory transactions */
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+ early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val);
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+ val &= 0xffff0000;
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+ val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
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+ early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val);
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+
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+}
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+
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+void __init pq2_find_bridges(void)
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+{
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+ extern int pci_assign_all_busses;
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+ struct pci_controller * hose;
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+ int host_bridge;
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+
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+ pci_assign_all_busses = 1;
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+
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+ hose = pcibios_alloc_controller();
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+
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+ if (!hose)
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+ return;
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+
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+ ppc_md.pci_swizzle = common_swizzle;
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+
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+ hose->first_busno = 0;
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+ hose->bus_offset = 0;
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+ hose->last_busno = 0xff;
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+
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+#ifdef CONFIG_ADS8272
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+ hose->set_cfg_type = 1;
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+#endif
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+
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+ setup_m8260_indirect_pci(hose,
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+ (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
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+ (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
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+
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+ /* Make sure it is a supported bridge */
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+ early_read_config_dword(hose,
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+ 0,
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+ PCI_DEVFN(0,0),
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+ PCI_VENDOR_ID,
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+ &host_bridge);
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+ switch (host_bridge) {
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+ case PCI_DEVICE_ID_MPC8265:
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+ break;
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+ case PCI_DEVICE_ID_MPC8272:
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+ break;
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+ default:
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+ printk("Attempting to use unrecognized host bridge ID"
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+ " 0x%08x.\n", host_bridge);
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+ break;
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+ }
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+
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+ pq2ads_setup_pci(hose);
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+
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+ hose->io_space.start = M82xx_PCI_LOWER_IO;
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+ hose->io_space.end = M82xx_PCI_UPPER_IO;
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+ hose->mem_space.start = M82xx_PCI_LOWER_MEM;
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+ hose->mem_space.end = M82xx_PCI_UPPER_MMIO;
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+ hose->pci_mem_offset = M82xx_PCI_MEM_OFFSET;
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+
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+ isa_io_base =
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+ (unsigned long) ioremap(M82xx_PCI_IO_BASE,
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+ M82xx_PCI_IO_SIZE);
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+ hose->io_base_virt = (void *) isa_io_base;
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+
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+ /* setup resources */
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+ pci_init_resource(&hose->mem_resources[0],
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+ M82xx_PCI_LOWER_MEM,
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+ M82xx_PCI_UPPER_MEM,
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+ IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");
|
|
|
+
|
|
|
+ pci_init_resource(&hose->mem_resources[1],
|
|
|
+ M82xx_PCI_LOWER_MMIO,
|
|
|
+ M82xx_PCI_UPPER_MMIO,
|
|
|
+ IORESOURCE_MEM, "PCI memory");
|
|
|
+
|
|
|
+ pci_init_resource(&hose->io_resource,
|
|
|
+ M82xx_PCI_LOWER_IO,
|
|
|
+ M82xx_PCI_UPPER_IO,
|
|
|
+ IORESOURCE_IO | 1, "PCI I/O");
|
|
|
+
|
|
|
+ ppc_md.pci_exclude_device = pq2pci_exclude_device;
|
|
|
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
|
|
|
+
|
|
|
+ ppc_md.pci_map_irq = pq2pci_map_irq;
|
|
|
+ ppc_md.pcibios_fixup = NULL;
|
|
|
+ ppc_md.pcibios_fixup_bus = NULL;
|
|
|
+
|
|
|
+}
|
Vitaly Bordug