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@@ -74,6 +74,7 @@
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#include "iwl-shared.h"
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#include "iwl-eeprom.h"
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#include "iwl-agn-hw.h"
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+#include "iwl-core.h"
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static int iwl_trans_rx_alloc(struct iwl_trans *trans)
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{
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@@ -631,13 +632,95 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans)
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~APMG_PS_CTRL_MSK_PWR_SRC);
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}
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+/*
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+ * Start up NIC's basic functionality after it has been reset
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+ * (e.g. after platform boot, or shutdown via iwl_apm_stop())
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+ * NOTE: This does not load uCode nor start the embedded processor
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+ */
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+static int iwl_apm_init(struct iwl_trans *trans)
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+{
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+ int ret = 0;
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+ IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
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+
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+ /*
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+ * Use "set_bit" below rather than "write", to preserve any hardware
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+ * bits already set by default after reset.
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+ */
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+
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+ /* Disable L0S exit timer (platform NMI Work/Around) */
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+ iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
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+ CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
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+
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+ /*
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+ * Disable L0s without affecting L1;
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+ * don't wait for ICH L0s (ICH bug W/A)
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+ */
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+ iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
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+ CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
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+
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+ /* Set FH wait threshold to maximum (HW error during stress W/A) */
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+ iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
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+
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+ /*
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+ * Enable HAP INTA (interrupt from management bus) to
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+ * wake device's PCI Express link L1a -> L0s
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+ */
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+ iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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+ CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
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+
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+ bus_apm_config(bus(trans));
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+
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+ /* Configure analog phase-lock-loop before activating to D0A */
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+ if (cfg(trans)->base_params->pll_cfg_val)
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+ iwl_set_bit(trans, CSR_ANA_PLL_CFG,
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+ cfg(trans)->base_params->pll_cfg_val);
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+
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+ /*
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+ * Set "initialization complete" bit to move adapter from
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+ * D0U* --> D0A* (powered-up active) state.
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+ */
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+ iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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+
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+ /*
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+ * Wait for clock stabilization; once stabilized, access to
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+ * device-internal resources is supported, e.g. iwl_write_prph()
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+ * and accesses to uCode SRAM.
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+ */
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+ ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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+ CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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+ CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
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+ if (ret < 0) {
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+ IWL_DEBUG_INFO(trans, "Failed to init the card\n");
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+ goto out;
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+ }
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+
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+ /*
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+ * Enable DMA clock and wait for it to stabilize.
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+ *
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+ * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
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+ * do not disable clocks. This preserves any hardware bits already
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+ * set by default in "CLK_CTRL_REG" after reset.
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+ */
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+ iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
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+ udelay(20);
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+
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+ /* Disable L1-Active */
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+ iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
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+ APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
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+
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+ set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
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+
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+out:
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+ return ret;
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+}
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+
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static int iwl_nic_init(struct iwl_trans *trans)
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{
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unsigned long flags;
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/* nic_init */
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spin_lock_irqsave(&trans->shrd->lock, flags);
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- iwl_apm_init(priv(trans));
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+ iwl_apm_init(trans);
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/* Set interrupt coalescing calibration timer to default (512 usecs) */
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iwl_write8(trans, CSR_INT_COALESCING,
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@@ -1267,6 +1350,9 @@ static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
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IWL_ERR(trans, "Error while preparing HW: %d", err);
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goto error;
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}
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+
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+ iwl_apm_init(trans);
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+
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return err;
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error:
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Emmanuel Grumbach