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@@ -23,7 +23,6 @@
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static unsigned long reset_value[OP_MAX_COUNTER];
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-static int num_counters;
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static int oprofile_running;
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static int mmcra_has_sihv;
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@@ -45,8 +44,6 @@ static void power4_reg_setup(struct op_counter_config *ctr,
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{
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int i;
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- num_counters = num_ctrs;
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-
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/*
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* SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above.
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* However we disable it on all POWER4 until we verify it works
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@@ -68,7 +65,7 @@ static void power4_reg_setup(struct op_counter_config *ctr,
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backtrace_spinlocks = sys->backtrace_spinlocks;
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- for (i = 0; i < num_counters; ++i)
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+ for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
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reset_value[i] = 0x80000000UL - ctr[i].count;
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/* setup user and kernel profiling */
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@@ -121,7 +118,7 @@ static void power4_start(struct op_counter_config *ctr)
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/* set the PMM bit (see comment below) */
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mtmsrd(mfmsr() | MSR_PMM);
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- for (i = 0; i < num_counters; ++i) {
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+ for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
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if (ctr[i].enabled) {
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ctr_write(i, reset_value[i]);
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} else {
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@@ -272,7 +269,7 @@ static void power4_handle_interrupt(struct pt_regs *regs,
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/* set the PMM bit (see comment below) */
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mtmsrd(mfmsr() | MSR_PMM);
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- for (i = 0; i < num_counters; ++i) {
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+ for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
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val = ctr_read(i);
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if (val < 0) {
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if (oprofile_running && ctr[i].enabled) {
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