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@@ -0,0 +1,235 @@
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+/*
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+ * r8a7779 Power management support
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+ *
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+ * Copyright (C) 2011 Renesas Solutions Corp.
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+ * Copyright (C) 2011 Magnus Damm
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+ *
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ */
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+
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+#include <linux/pm.h>
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+#include <linux/suspend.h>
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+#include <linux/err.h>
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+#include <linux/pm_clock.h>
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+#include <linux/platform_device.h>
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+#include <linux/delay.h>
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+#include <linux/irq.h>
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+#include <linux/interrupt.h>
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+#include <linux/console.h>
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+#include <asm/system.h>
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+#include <asm/io.h>
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+#include <mach/common.h>
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+#include <mach/r8a7779.h>
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+
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+static void __iomem *r8a7779_sysc_base;
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+
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+/* SYSC */
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+#define SYSCSR 0x00
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+#define SYSCISR 0x04
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+#define SYSCISCR 0x08
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+#define SYSCIER 0x0c
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+#define SYSCIMR 0x10
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+#define PWRSR0 0x40
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+#define PWRSR1 0x80
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+#define PWRSR2 0xc0
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+#define PWRSR3 0x100
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+#define PWRSR4 0x140
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+
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+#define PWRSR_OFFS 0x00
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+#define PWROFFCR_OFFS 0x04
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+#define PWRONCR_OFFS 0x0c
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+#define PWRER_OFFS 0x14
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+
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+#define SYSCSR_RETRIES 100
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+#define SYSCSR_DELAY_US 1
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+
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+#define SYSCISR_RETRIES 1000
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+#define SYSCISR_DELAY_US 1
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+
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+#ifdef CONFIG_PM
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+
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+static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch,
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+ int sr_bit, int reg_offs)
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+{
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+ int k;
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+
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+ for (k = 0; k < SYSCSR_RETRIES; k++) {
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+ if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit))
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+ break;
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+ udelay(SYSCSR_DELAY_US);
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+ }
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+
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+ if (k == SYSCSR_RETRIES)
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+ return -EAGAIN;
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+
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+ iowrite32(1 << r8a7779_ch->chan_bit,
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+ r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs);
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+
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+ return 0;
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+}
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+
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+static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch)
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+{
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+ return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS);
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+}
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+
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+static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch)
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+{
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+ return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS);
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+}
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+
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+static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
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+ int (*on_off_fn)(struct r8a7779_pm_ch *))
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+{
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+ unsigned int isr_mask = 1 << r8a7779_ch->isr_bit;
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+ unsigned int chan_mask = 1 << r8a7779_ch->chan_bit;
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+ unsigned int status;
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+ int ret = 0;
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+ int k;
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+
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+ iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
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+
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+ do {
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+ ret = on_off_fn(r8a7779_ch);
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+ if (ret)
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+ goto out;
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+
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+ status = ioread32(r8a7779_sysc_base +
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+ r8a7779_ch->chan_offs + PWRER_OFFS);
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+ } while (status & chan_mask);
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+
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+ for (k = 0; k < SYSCISR_RETRIES; k++) {
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+ if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask)
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+ break;
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+ udelay(SYSCISR_DELAY_US);
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+ }
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+
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+ if (k == SYSCISR_RETRIES)
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+ ret = -EIO;
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+
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+ iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
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+
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+ out:
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+ pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n",
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+ r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0),
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+ ioread32(r8a7779_sysc_base + PWRSR1),
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+ ioread32(r8a7779_sysc_base + PWRSR2),
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+ ioread32(r8a7779_sysc_base + PWRSR3),
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+ ioread32(r8a7779_sysc_base + PWRSR4), ret);
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+ return ret;
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+}
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+
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+static int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch)
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+{
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+ return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off);
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+}
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+
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+static int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch)
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+{
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+ return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on);
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+}
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+
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+static void __init r8a7779_sysc_init(void)
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+{
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+ r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE);
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+ if (!r8a7779_sysc_base)
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+ panic("unable to ioremap r8a7779 SYSC hardware block\n");
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+
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+ /* enable all interrupt sources, but do not use interrupt handler */
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+ iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER);
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+ iowrite32(0, r8a7779_sysc_base + SYSCIMR);
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+}
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+
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+static int pd_power_down(struct generic_pm_domain *genpd)
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+{
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+ return r8a7779_sysc_power_down(to_r8a7779_ch(genpd));
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+}
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+
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+static int pd_power_up(struct generic_pm_domain *genpd)
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+{
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+ return r8a7779_sysc_power_up(to_r8a7779_ch(genpd));
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+}
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+
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+static bool pd_is_off(struct generic_pm_domain *genpd)
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+{
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+ struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd);
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+ unsigned int st;
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+
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+ st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS);
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+ if (st & (1 << r8a7779_ch->chan_bit))
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+ return true;
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+
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+ return false;
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+}
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+
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+static bool pd_active_wakeup(struct device *dev)
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+{
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+ return true;
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+}
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+
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+void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
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+{
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+ struct generic_pm_domain *genpd = &r8a7779_pd->genpd;
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+
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+ pm_genpd_init(genpd, NULL, false);
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+ genpd->dev_ops.stop = pm_clk_suspend;
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+ genpd->dev_ops.start = pm_clk_resume;
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+ genpd->dev_ops.active_wakeup = pd_active_wakeup;
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+ genpd->dev_irq_safe = true;
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+ genpd->power_off = pd_power_down;
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+ genpd->power_on = pd_power_up;
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+
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+ if (pd_is_off(&r8a7779_pd->genpd))
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+ pd_power_up(&r8a7779_pd->genpd);
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+}
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+
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+void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
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+ struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+
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+ pm_genpd_add_device(&r8a7779_pd->genpd, dev);
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+ if (pm_clk_no_clocks(dev))
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+ pm_clk_add(dev, NULL);
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+}
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+
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+struct r8a7779_pm_domain r8a7779_sh4a = {
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+ .ch = {
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+ .chan_offs = 0x80, /* PWRSR1 .. PWRER1 */
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+ .isr_bit = 16, /* SH4A */
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+ }
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+};
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+
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+struct r8a7779_pm_domain r8a7779_sgx = {
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+ .ch = {
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+ .chan_offs = 0xc0, /* PWRSR2 .. PWRER2 */
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+ .isr_bit = 20, /* SGX */
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+ }
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+};
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+
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+struct r8a7779_pm_domain r8a7779_vdp1 = {
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+ .ch = {
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+ .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */
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+ .isr_bit = 21, /* VDP */
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+ }
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+};
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+
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+struct r8a7779_pm_domain r8a7779_impx3 = {
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+ .ch = {
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+ .chan_offs = 0x140, /* PWRSR4 .. PWRER4 */
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+ .isr_bit = 24, /* IMP */
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+ }
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+};
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+
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+#else /* CONFIG_PM */
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+
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+static inline void r8a7779_sysc_init(void) {}
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+
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+#endif /* CONFIG_PM */
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+
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+void __init r8a7779_pm_init(void)
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+{
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+ r8a7779_sysc_init();
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+}
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Magnus Damm