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@@ -66,68 +66,11 @@ void smp_thermal_interrupt(struct pt_regs *regs)
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irq_exit();
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}
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-static void intel_set_thermal_handler(void)
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+void intel_set_thermal_handler(void)
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{
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vendor_thermal_interrupt = intel_thermal_interrupt;
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}
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-/* P4/Xeon Thermal regulation detect and init: */
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-static void intel_init_thermal(struct cpuinfo_x86 *c)
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-{
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- unsigned int cpu = smp_processor_id();
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- int tm2 = 0;
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- u32 l, h;
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-
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- /* Thermal monitoring depends on ACPI and clock modulation*/
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- if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
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- return;
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-
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- /*
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- * First check if its enabled already, in which case there might
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- * be some SMM goo which handles it, so we can't even put a handler
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- * since it might be delivered via SMI already:
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- */
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- rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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- h = apic_read(APIC_LVTTHMR);
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- if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
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- printk(KERN_DEBUG
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- "CPU%d: Thermal monitoring handled by SMI\n", cpu);
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- return;
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- }
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-
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- if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))
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- tm2 = 1;
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-
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- /* Check whether a vector already exists */
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- if (h & APIC_VECTOR_MASK) {
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- printk(KERN_DEBUG
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- "CPU%d: Thermal LVT vector (%#x) already installed\n",
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- cpu, (h & APIC_VECTOR_MASK));
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- return;
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- }
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-
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- /* We'll mask the thermal vector in the lapic till we're ready: */
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- h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
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- apic_write(APIC_LVTTHMR, h);
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-
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- rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
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- wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
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-
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- intel_set_thermal_handler();
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-
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- rdmsr(MSR_IA32_MISC_ENABLE, l, h);
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- wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
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-
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- /* Unmask the thermal vector: */
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- l = apic_read(APIC_LVTTHMR);
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- apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
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-
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- printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",
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- cpu, tm2 ? "TM2" : "TM1");
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-
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- /* enable thermal throttle processing */
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- atomic_set(&therm_throt_en, 1);
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-}
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#endif /* CONFIG_X86_MCE_P4THERMAL */
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/* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */
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